Test_Pattern_Status; Lane_0_Error_Code; Lane_1_Error_Code; Lane_2_Error_Code - Texas Instruments TLK3134 Data Manual

TLK3134
SLLS838F – MAY 2007 – REVISED DECEMBER 2009
ADDRESS: 0x8021
BIT(s)
Test pattern sync
4/5/32801.15
status
ADDRESS: 0x8022
BIT(s)
Lane 0 error code
4/5.32802.15:7
select.
ADDRESS: 0x8023
BIT(s)
Lane 1 error code
4/5.32803.15:7
select.
ADDRESS: 0x8024
BIT(s)
Lane 2 error code
4/5.32804.15:7
select.
ADDRESS: 0x8025
BIT(s)
Lane 3 error code
4/5.32805.15:7
select.
ADDRESS: 0x8026
BIT(s)
4/5.32806. 15 Lane 3 phase shift
4/5.32806. 14 Lane 2 phase shift
4/5.32806. 13 Lane 1 phase shift
4/5.32806. 12 Lane 0 phase shift
60 Detailed Description
Table 2-64. TEST_PATTERN_STATUS
NAME
When high, indicates that preamble for 10GFC_CJPAT/CRPAT/CJPAT
has been recovered.
Table 2-65. LANE_0_ERROR_CODE
NAME
Error code to be transmitted in case of error condition. This applies to
both TX and RX data paths. The msb is the control bit; remaining 8 bits
constitute the error code. The default value for lane 0 corresponds to
8'h9C with the control bit being 1'b1. The default values for lanes 0~3
correspond to ||LF||
Table 2-66. LANE_1_ERROR_CODE
NAME
Error code to be transmitted in case of error condition. This applies to
both TX and RX data paths. The msb is the control bit; remaining 8 bits
constitute the error code. The default value for lane 1 corresponds to
8'h00 with the control bit being 1'b0. The default values for lanes 0~3
correspond to ||LF||
Table 2-67. LANE_2_ERROR_CODE
NAME
Error code to be transmitted in case of error condition. This applies to
both TX and RX data paths. The msb is the control bit; remaining 8 bits
constitute the error code. The default value for lane 2 corresponds to
8'h00 with the control bit being 1'b0. The default values for lanes 0~3
correspond to ||LF||
Table 2-68. LANE_3_ERROR_CODE
NAME
Error code to be transmitted in case of error condition. This applies to
both TX and RX data paths. The msb is the control bit; remaining 8 bits
constitute the error code. The default value for lane 3 corresponds to
8'h01 with the control bit being 1'b0. The default values for lanes 0~3
correspond to ||LF||
Table 2-69. RX_PHASE_SHIFT_CONTROL
NAME
When set, delays the RX data sent to the XGMII interface by one clock
cycle. (Default 1'b0)
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DEFAULT: 0x0000
DESCRIPTION
DEFAULT: 0xCE00
DESCRIPTION
DEFAULT: 0x0000
DESCRIPTION
DEFAULT: 0x0000
DESCRIPTION
DEFAULT: 0x0080
DESCRIPTION
DEFAULT: 0x0000
DESCRIPTION
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