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Texas Instruments CC1021 Manual

Single-chip low-power rf transceiver for narrowband systems
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CC1021 Single-Chip Low-Power RF Transceiver for Narrowband Systems
1 Device Overview
1.1
Features
1
• True Single-Chip UHF RF Transceiver
• Frequency Range 402 MHz to 470 MHz and
804 MHz to 930 MHz
• High Sensitivity
– Up to –112 dBm for 38.4 kHz Receiver Channel
Filter Bandwidth
– Up to –106 dBm for 102.4 kHz Receiver
Channel Filter Bandwidth
• Programmable Output Power
• Low Current Consumption
– RX: 19.9 mA
• Low Supply Voltage
– From 2.3 V to 3.6 V
• Very Few External Components Required
• Small Size
– QFN 32 Package
1.2
Applications
•
Low-Power UHF Wireless Data Transmitters and
Receivers With Channel Spacings
of 50 kHz or Higher
•
433-, 868-, 915-, 930-MHz ISM/SRD Band
Systems
1.3
Description
The CC1021 device is a true single-chip UHF transceiver designed for very low power and very low
voltage wireless applications. The circuit is mainly intended for the ISM (Industrial, Scientific and Medical)
and SRD (Short Range Device) frequency bands at 433 MHz, 868 MHz, and 915 MHz, but can easily be
programmed for multichannel operation at other frequencies in the 402- to 470-MHz and 804- to 930-MHz
range.
The CC1021 device is especially suited for narrowband systems with channel spacing of 50 kHz and
higher complying with EN 300 220 and CC CFR47 part 15.
The CC1021 device main operating parameters can be programmed through a serial bus, thus making the
CC1021 device a very flexible and easy to use transceiver.
In a typical system, the CC1021 device is used together with a microcontroller and a few external passive
components.
PART NUMBER
CC1021
(1) For more information, see
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Order
Product
Technical
Folder
Now
Documents
Not Recommended for New Designs NRND
Table 1-1. Device Information
VQFNP (32)
Section
8, Mechanical Packaging and Orderable Information.
Tools &
Software
SWRS045F – JANUARY 2006 – REVISED NOVEMBER 2018
• Pb-Free Package
• Digital RSSI and Carrier Sense Indicator
• Data Rate Up to 153.6 kBaud
• OOK, FSK, and GFSK Data Modulation
• Integrated Bit Synchronizer
• Image Rejection Mixer
• Programmable Frequency
• Automatic Frequency Control (AFC)
• Suitable for Frequency Hopping Systems
• Suited for Systems Targeting Compliance With
EN 300 220 and FCC CFR47 Part 15
• Easy-to-Use Software for Generating the CC1021
Configuration Data
• Fully Compatible With CC1020 for Receiver
Channel Filter Bandwidths of 38.4 kHz and Higher
•
AMR – Automatic Meter Reading
•
Wireless Alarm and Security Systems
•
Home Automation
•
Low-Power Telemetry
•
Automotive (RKE/TPMS)
(1)
PACKAGE
Support &
Community
BODY SIZE (NOM)
7.00 mm × 7.00 mm
CC1021

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Summary of Contents for Texas Instruments CC1021

  • Page 1 The CC1021 device main operating parameters can be programmed through a serial bus, thus making the CC1021 device a very flexible and easy to use transceiver. In a typical system, the CC1021 device is used together with a microcontroller and a few external passive components.

  • Page 2: Device Overview

    Not Recommended for New Designs NRND CC1021 SWRS045F – JANUARY 2006 – REVISED NOVEMBER 2018 www.ti.com Functional Block Diagram Figure 1-1 shows the system block diagram of the CC1021 device. DIGITAL DEMODULATOR - Digital RSSI RF_IN LNA 2 - Gain Control...

  • Page 3: Table Of Contents

    Changes from August 20, 2016 to November 30, 2018 Page ..............• Global: Changed upper frequency from 960 MHz to 930 MHz .................. • Global: Removed references to ARIB STD-T96 Revision History Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...

  • Page 4: Terminal Configuration And Functions

    SWRS045F – JANUARY 2006 – REVISED NOVEMBER 2018 www.ti.com 3 Terminal Configuration and Functions Pin Diagram Figure 3-1 shows pin names and locations for the CC1021 device. 32 31 30 29 28 27 26 25 PCLK 1 PDI 2 AVDD...
  • Page 5 Power supply connection (3 V typical) for digital modules Programming chip select, active low, for configuration interface. Internal pullup PSEL Digital input resistor. Terminal Configuration and Functions Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...

  • Page 6: Specifications

    Binary FSK specified separation at 1.84 MHz frequency reference frequency. Larger in 804 to 930 MHz range separation separations can be achieved at higher reference frequencies. Specifications Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 7 Spurious Emission (SWRA057) presents and discusses a solution that reduces the TX mode spurious emission close to 862 MHz by increasing the REF_DIV from 1 to 7. Specifications Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...

  • Page 8: Rf Receive

    –11 sensitivity level, CW jammer at 102.4 kHz channel filter BW −3 operating frequency, BER = 10 (1) Two tone test (+10 MHz and +20 MHz) Specifications Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 9 Ω Receive mode. See Section 5.11 Input impedance for details. 868 MHz 54 – j22 Ω (2) Close-in spurious response rejection. (3) Out-of-band spurious response rejection. Specifications Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...

  • Page 10: Rssi / Carrier Sense

    102.4 kHz channel filter BW, signal at ±100 kHz and ±200 kHz offset 868 MHz and observe at which level carrier sense ±200 kHz –44 is indicated. Specifications Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...

  • Page 11: Intermediate Frequency (If)

    External clock signal drive, full-swing digital external clock 0 – VDD Set XOSC_BYPASS = 1 in the INTERFACE register when using a full-swing digital external clock. Specifications Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...

  • Page 12: Frequency Synthesizer

    TX mode, minimum time DIO must be ready before DIO setup time the positive edge of DCLK. Data should be set up on the negative edge of DCLK. Specifications Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...

  • Page 13: Current Consumption

    Current Consumption, crystal oscillator and bias µA 14.7456 MHz, 16 pF load crystal Current Consumption, crystal oscillator, bias and synthesizer 14.7456 MHz, 16 pF load crystal Specifications Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...

  • Page 14: Thermal Resistance Characteristics For Vqfnp

    JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements Power dissipation of 2 W and an ambient temperature of 70ºC is assumed. Specifications Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...

  • Page 15: Detailed Description

    Figure 5-1. Only signal pins are shown. The CC1021 device features a low-IF receiver. The received RF signal is amplified by the low-noise amplifier (LNA and LNA2) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF, the I/Q signal is complex filtered and amplified, and then digitized by the ADCs. Automatic gain control, fine channel filtering, demodulation and bit synchronization is performed digitally.

  • Page 16: Configuration Overview

    These hexadecimal numbers will then be the necessary input to the microcontroller for the configuration of the CC1021 device. In addition, the program will provide the user with the component values needed for the input/output matching circuit, the PLL loop filter and the LC filter.

  • Page 17: Microcontroller Interface

    SWRS045F – JANUARY 2006 – REVISED NOVEMBER 2018 Microcontroller Interface Used in a typical system, the CC1021 device will interface to a microcontroller. This microcontroller must be able to: • Program the CC1021 device into different modes via the 4-wire serial configuration interface (PDI, PDO, PCLK and PSEL) •...

  • Page 18: 4-Wire Serial Configuration Interface

    The configuration registers can also be read by the microcontroller via the same configuration interface. The seven address bits are sent first, then the R/W bit set low to initiate the data read-back. The CC1021 device then returns the data from the addressed register. PDO is used as the data output and must be configured as an input by the microcontroller.
  • Page 19 (1) The setup and hold times refer to 50% of VDD. The rise and fall times refer to 10% / 90% of VDD. The maximum load that this table is valid for is 20 pF. Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...

  • Page 20: Signal Interface

    In transmit mode, the CC1021 device provides the data clock at DCLK and DIO is used as data input. Data is clocked into the CC1021 device at the rising edge of DCLK. The data is modulated at RF without encoding.
  • Page 21 In the Synchronous Manchester encoded mode, the CC1021 device uses Manchester coding when modulating the data. The CC1021 device also performs the data decoding and synchronization. The Manchester code is based on transitions; a “0” is encoded as a low-to-high transition, a “1” is encoded as a high-to-low transition.
  • Page 22 In asynchronous transparent UART mode, any data rate up to 153.6 kBaud can be used. Table 5-2. DIV2 for Different Settings of MCLK_DIV2 MCLK_DIV2[1:0] DIV2 Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 23 CRYSTAL FREQUENCY [MHz] DATA RATE [kBaud] 4.9152 7.3728 9.8304 12.288 14.7456 17.2032 19.6608 0.45 4.096 8.192 14.4 16.384 19.2 28.8 32.768 38.4 57.6 65.536 76.8 115.2 153.6 Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 24 × TXDEV_M × 2 (10) OOK (On-Off Keying) is used if TXDEV_M[3:0] = 0000. The TX_SHAPING bit in the DEVIATION register controls Gaussian shaping of the modulation signal. Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 25 (SBW) can be approximated by (Carson’s rule) as shown in Equation SBW = 2 × f + 2 × frequency deviation (13) Where: f is the modulating signal. Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 26 [decimal(binary)] 38.4 7 (111b) 43.9 6 (110b) 51.2 5 (101b) 61.4 4 (100b) 76.8 3 (011b) 102.4 2 (010b) 153.6 1 (001b) 307.2 0 (000b) Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 27 The digital data slicer in the CC1021 device uses an average value of the minimum and maximum frequency deviation detected as the comparison level. The RXDEV_X[1:0] and RXDEV_M[3:0] in the AFC_CONTROL register are used to set the expected deviation of the incoming signal.
  • Page 28 –94 5.9.5 RSSI The CC1021 device has a built-in RSSI (Received Signal Strength Indicator) giving a digital value that can be read form the RSSI register. The RSSI reading must be offset and adjusted for VGA gain setting (VGA_SETTING[4:0] in the VGA3 register).
  • Page 29 Figure 5-11. Typical RSSI Value vs Input Power for Different Figure 5-12. Typical RSSI Value vs Input Power for Different Channel Filter Bandwidths, 433 MHz Channel Filter Bandwidths, 868 MHz Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 30 DP = DX else if DP < –DX then set DP = –DX. 16. Set XP = XP + DP. 17. Write XP to PHASE_COMP register. Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 31 The image rejection is reduced for low supply voltages (typically < 2.5 V) when operating in the 402 to 470 MHz frequency range. Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 32 Figure 5-15. Typical Blocker Rejection. Carrier Frequency Set to 868.3072 MHz (102.4 kHz Channel Filter Bandwidth, 38.4 kBaud) 868.3072 MHz (102.4 kHz Channel Filter Bandwidth, 19.2 kBaud) Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 33 5.9.8 Linear IF Chain and AGC Settings The CC1021 device is based on a linear IF chain where the signal amplification is done in an analog VGA (Variable Gain Amplifier). The gain is controlled by the digital part of the IF chain after the ADC (Analog to Digital Converter).
  • Page 34 AGC settling time and receiver sensitivity because the AGC settling time can be reduced for data rates lower than 76.8 kBaud by using a wider receiver channel filter bandwidth (that is, larger ChBW). Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 35 4. In general the first bit of sync should be opposite of last bit in preamble, to achieve one more transition. The recommended sync words for the CC1021 device are 2 bytes (D391), 3 bytes (D391DA) or 4 bytes (D391DA26) and are selected as the best compromise of the above criteria.
  • Page 36 By setting SEQ_PD = 1 in the MAIN register, the CC1021 device is set in power down mode. If SEQ_PSEL = 1 in the SEQUENCING register the automatic power-up sequence is initiated by a negative transition on the PSEL pin.
  • Page 37 2 (ADC _ DIV [2 : 0] ´ ADC clock (ADC_CLK): where ADC_DIV[2:0] is set in the MODEM register. Figure 5-18. Automatic Power-Up Sequencing Flow Chart Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 38 TX_SHAPING bit in the DEVIATION register enables the GFSK. Figure 5-19 shows a typical eye diagram for 153.6 kBaud data rate at 868 MHz operation. Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 39 The user should therefore add a delay equivalent to at least 2 bits after the data payload has been transmitted before switching off the PA (that is, before stopping the transmission). Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 40 Modulation bandwidth and spurious emission are normally measured with the PA continuously on and a repeated test sequence. In cases where the modulation bandwidth and spurious emission are measured with the CC1021 device switching from power down mode to TX mode, a PA ramping sequence could be used to minimize modulation bandwidth and spurious emission.
  • Page 41 AVDD = 3 V ANTENNA CC1021 RF_OUT RF_IN SWITCH Figure 5-22. Input and Output Matching Network Figure 5-23. Typical LNA Input Impedance, 200 to 1000 MHz Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 42 Table 5-9 Table 5-9. Impedances at the First 5 Harmonics (433 MHz Matching Network) FREQUENCY REAL IMAGINARY (MHz) (Ohms) (Ohms) 1299 –563 1732 –123 2165 –66 Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 43 Values are listed in Table 5-10 Table 5-10. Impedances at the First 3 Harmonics (868/915 MHz Matching Network) FREQUENCY REAL IMAGINARY (MHz) (Ohms) (Ohms) 1736 1830 2604 2745 Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 44 The PLL_BW can be found from Equation æ ö ç ÷ PLL _ BW 16 log ç ÷ 7.126 è ø (31) Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 45 • VCO currents are equal (VCO_CURRENT_A[3:0] = VCO_CURRENT_B[3:0] in the VCO register). The CAL_DUAL bit in the CALIBRATE register controls dual or separate calibration. Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 46 There is a finite possibility that the PLL self-calibration will fail. The calibration routine in the source code should include a loop so that the PLL is re-calibrated until PLL lock is achieved if the PLL does not lock the first time. Refer to CC1021 Errata Note 002, available in the CC1021 product folder.
  • Page 47 Up to 153.6 kBaud data rate — (500 kHz) ±50 kHz settling accuracy (1) 1) 307.2 kHz step, 2) step as given in brackets, 3) 1 MHz step Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 48 Registers can be programmed freely in any order. The CC1021 device should then be calibrated in both RX and TX mode. After this is completed, the CC1021 device is ready for use. See the detailed procedure flowcharts in...
  • Page 49 Calibrate VCO and PLL MAIN: PD_MODE=1, FS_PD=1, MAIN: PD_MODE=1, FS_PD=1, XOSC_PD=1, BIAS_PD=1 XOSC_PD=1, BIAS_PD=1 PA_POWER=00h PA_POWER=00h Power Down mode Power Down mode Figure 5-27. Initializing Sequence Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 50 Baud rate for data rates up to 9.6 kBaud. For the highest data rates the channel bandwidth must be 2 times the Baud rate (see Table 5-14). Manchester coding must always be used for OOK. Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 51 14.7456, 17.2032, 19.6608 MHz will give accurate data rates as shown in Table 5-4 and an IF frequency of 307.2 kHz. The crystal frequency will influence the programming of the CLOCK_A, CLOCK_B and MODEM registers. Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 52 Table 5-15. Crystal Oscillator Component Values ITEM = 12 pF = 16 pF = 22 pF 6.8 pF 15 pF 27 pF 6.8 pF 15 pF 27 pF Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 53 SWRS045F – JANUARY 2006 – REVISED NOVEMBER 2018 5.17 Built-in Test Pattern Generator The CC1021 device has a built-in test pattern generator that generates a PN9 pseudo random sequence. The PN9_ENABLE bit in the MODEM register enables the PN9 generator. A transition on the DIO pin is required after enabling the PN9 pseudo random sequence.
  • Page 54 5.18.2 Interrupt Upon Received Signal Carrier Sense In synchronous mode, the DCLK pin on the CC1021 device can also be used to give an interrupt signal to the microcontroller when the RSSI level exceeds a certain threshold (carrier sense threshold). This function can be used to wake or interrupt the microcontroller when a strong signal is received.
  • Page 55 (Short Range Devices) for license free operation are allowed to operate in the 433 and 868 to 870 MHz bands in most European countries. In the United States, such devices operate in the 260 to 470 and 902 to 928 MHz bands. Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 56 A narrowband preselector filter is not necessary to achieve image rejection. A unique feature in the CC1021 device is the very fine frequency resolution. This can be used for temperature compensation of the crystal if the temperature drift curve is known and a temperature sensor is included in the system.
  • Page 57 5.20.6 Frequency Hopping Spread Spectrum Systems (FHSS) Due to the very fast locking properties of the PLL, the CC1021 device is also very suitable for frequency hopping systems. Hop rates of 1 to 100 hops/s are commonly used depending on the bit rate and the amount of data to be sent during each transmission.
  • Page 58 5.21 Antenna Considerations The CC1021 device can be used together with various types of antennas. The most common antennas for short-range communication are monopole, helical and loop antennas. Monopole antennas are resonant antennas with a length corresponding to one quarter of the electrical wavelength ( ).
  • Page 59 SWRS045F – JANUARY 2006 – REVISED NOVEMBER 2018 5.22 Configuration Registers The configuration of the CC1021 device is done by programming the 8-bit configuration registers. The configuration data based on selected system parameters are most easily found by using the SmartRF™...
  • Page 60 Not Recommended for New Designs NRND CC1021 SWRS045F – JANUARY 2006 – REVISED NOVEMBER 2018 www.ti.com Table 5-16. CC1021 Device Register Overview (continued) ADDRESS ACRONYM REGISTER NAME TEST5 Test register for ADC testing TEST6 Test register for VGA testing TEST7...
  • Page 61 1: LNA_EN pin is “1” when activating external LNA (1) If TF_ENABLE=1 or TA_ENABLE=1 in TEST4 register, then INTERFACE[3:0] controls analog test module: INTERFACE[3] = TEST_PD, INTERFACE[2:0] = TEST_MODE[2:0]. Otherwise, TEST_PD=1 and TEST_MODE[2:0]=001. Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 62 Reset calibration logic and lock detector (1) For reset of the CC1021 device, write RESET_N=0 in the MAIN register. The reset register should not be used during normal operation. (2) Bits in the RESET register are self-clearing (will be set to 1 when the reset operation starts). Relevant digital clocks must be running for the resetting to complete.
  • Page 63 8 MSB of frequency control word B Table 5-27. FREQ_1B Register (09h) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE FREQ_1B[7:0] FREQ_B[14:7] — 8 MSB of frequency control word B Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 64 Recommended setting: VCO_CURRENT_A=4 VCO[3:0] VCO_CURRENT_B[3:0] — Control of current in VCO core for frequency B The current steps are the same as for VCO_CURRENT_A Recommended setting: VCO_CURRENT_B=4 Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 65 TXDEV_M = deviation × 2 in 804 to 930 MHz band, Decrease TXDEV_X and try again if TXDEV_M < 8. Increase TXDEV_X and try again if TXDEV_M ≥ 16. Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 66 6: Decimation clock divisor = 7, 43.9 kHz channel filter BW. 31: Decimation clock divisor = 8, 38.4 kHz channel filter BW. Channel filter bandwidth is 307.2 kHz divided by the decimation clock divisor. Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 67 Recommended setting: LNA2_MIN=0 for best selectivity. VGA2[6] LNA2_MAX — Maximum LNA2 setting used in VGA 0: Medium LNA2 gain 1: Maximum LNA2 gain Recommended setting: LNA2_MAX=1 for best sensitivity. Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 68 This is also the maximum gain that the AGC is allowed to use. Figure 5-17 for an explanation of the relationship between RSSI, AGC and carrier sense settings. Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 69 3: Declare lock at counter value 1023, out of lock at value 1007 (1) Set LOCK_SELECT=2 to use the LOCK pin as a lock indicator. Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 70 1: Long reset delay Recommended setting: PD_LONG=0. ANALOG[3] — — Reserved, write 0 ANALOG[2] PA_BOOST Boost PA bias current for higher output power Recommended setting: PA_BOOST=1. Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 71 LO buffer current, in TX (to PA driver) 0: Minimum buffer current … 7: Maximum buffer current Recommended settings: TX_CURRENT=2 for 402 to 470 MHz, TX_CURRENT=5 for 804 to 930 MHz. Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 72 It is more efficient in terms of current consumption to use either the lower or upper 4-bits in the PA_POWER register to control the power. Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 73 Table 5-51. TEST1 Register (21h, for Test Only) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE TEST1[7:4] CAL_DAC_OPEN[3:0] — Calibration DAC override value, active when BREAK_LOOP=1 TEST1[3:0] CHP_CO[3:0] — Charge pump current override value Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 74 Outputs ADC samples on LOCK and DIO, while ADC_CLK is output on DCLK TEST5[4] CHOP_DISABLE Disable chopping in ADC integrators TEST5[3] SHAPING_DISABLE Disable ADC feedback mismatch shaping TEST5[2] VCM_ROT_DISABLE Disable rotation for VCM mismatch shaping Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 75 Carrier sense when RSSI is above CS_LEVEL STATUS[2] LOCK — Logical level on LOCK pin STATUS[1] DCLK — Logical level on DCLK pin STATUS[0] — Logical level on DIO pin Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 76 NAME ACTIVE DESCRIPTION VALUE STATUS1[7:4] CAL_DAC[3:0] — — Status vector defining applied Calibration DAC value STATUS1[3:0] CHP_CURRENT[3:0] — — Status vector defining applied CHP_CURRENT value Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 77 — — — Not in use, will read 0 STATUS7[4:0] VGA_GAIN_OFFSET[4:0] — — Readout of offset between VGA_SETTING and actual VGA gain set by AGC Detailed Description Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 78 Customers should validate and test their design implementation to confirm system functionality. Application Information Very few external components are required for the operation of the CC1021 device. The recommended application circuit is shown in Figure 6-1.
  • Page 79 Precision resistor for current reference generator PLL loop filter resistor PLL loop filter resistor PA output match, see Section 5.11 XTAL Crystal, see Section 5.16 Applications, Implementation, and Layout Copyright © 2006–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021...
  • Page 80 50 Ω. Internal circuitry makes it possible to connect the input and output together and match the CC1021 device to 50 Ω in both RX and TX mode. However, it is recommended to use an external T/R switch for optimum performance. See Section 5.11...
  • Page 81 Do not place a via underneath the CC1021 device at “pin #1 corner” as this pin is internally connected to the exposed die attached pad, which is the main ground connection for the chip.
  • Page 82 To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. Each device has one of three prefixes: X, P, or null (no prefix) (for example, CC1021 is in production; therefore no prefix is assigned).
  • Page 83 SmartRF, E2E are trademarks of Texas Instruments. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 84 Ball material (4/5) CC1021RSSR ACTIVE 2500 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 85 CC1021 CC1021RSST ACTIVE RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 85 CC1021 The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
  • Page 85 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 Addendum-Page 2...
  • Page 86 PACKAGE MATERIALS INFORMATION www.ti.com 10-Mar-2021 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) CC1021RSSR 2500 330.0 16.4 12.0 16.0 Pack Materials-Page 1...
  • Page 87 PACKAGE MATERIALS INFORMATION www.ti.com 10-Mar-2021 *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) CC1021RSSR 2500 350.0 350.0 43.0 Pack Materials-Page 2...
  • Page 90 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2021, Texas Instruments Incorporated...

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