Jc_Pll_Control; Jc_Test_Control_1; Jc_Test_Control_2; Jc_Ti_Test_Control_1 - Texas Instruments TLK3134 Data Manual

4-channel multi-rate transceiver
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ADDRESS: 0x9107
BIT(s)
NAME
4/5.37127.15
JC_EN_PLL
4/5.37127.14:12 VCO_BIAS_CTRL[2:0]
VCO_CAPBANK_CTRL[3:0
4/5.37127.11:8
]
4/5.37127.7
DIFFTX_EN
4/5.37127.6
DIFFRX_EN
4/5.37127.5:4
PFD_CTRL[1:0]
4/5.37127.3
AD_SEL_TST
4/5.37127.2
REFCLK_CML_EN
ADDRESS: 0x9108
BIT(s)
NAME
4/5.37128.15:12 REFCK_DIV_TST[3:0]
4/5.37128.11:8
FB_DIV_TST[3:0]
4/5.37128.7:4
TXRX_DIV_TST[3:0]
4/5.37128.3:2
RXBCLK_DIV_TST[1:0]
(1) This register value should be written 0x00A0 when JC PLL is used
ADDRESS: 0x9109
BIT(s)
NAME
4/5.37129.15:14 DEL_DIV_TST[1:0]
4/5.37129.13:12 HSTL_DIV_TST[1:0]
4/5.37129.11:10 HSTL_DIV2_TST[1:0]
4/5.37129.9:8
PFD_TST[1:0]
4/5.37129.7:4
CP_TST[3:0]
4/5.37129.3:0
CP_BUF_TST[3:0]
ADDRESS: 0x9150
BIT(s)
NAME
4/5.37200.15:8
CML_BIAS_TST[7:0]
4/5.37200.7:4
CML_BIAS_CTRL[3:0]
4/5.37200.3
DIFFTX_ENTST
4/5.37200.2
DIFFRX_ENTST
Copyright © 2007–2009, Texas Instruments Incorporated
Table 2-125. JC_PLL_CONTROL
0 = Disables Jitter Cleaner
1 = Enables Jitter Cleaner
Control bits for VCO tail current
Control bits for VCO band select
Enable signal for TX differential path
Enable signal for RX differential path
Control bits for phase frequency detector
Control bit to select either digital or analog TST_OUT
Enable signal for CML buffer inside output divider
Table 2-126. JC_TEST_CONTROL_1
Test bits for Reference divider
Test bits for Feedback divider
Test bits for TXRX output divider. Should be set to 4'b1010 when JC PLL
is used
Test bits for RXBYTECLK divider
Table 2-127. JC_TEST_CONTROL_2
Test bits for Delay clock divider
Test bits for HSTL VTP divider
Test bits for HSTL VTP 2X divider
Test bits for Phase frequency detector
Test bits for Charge pump
Test bits for Charge pump Buffer
Table 2-128. JC_TI_TEST_CONTROL_1
Test bits for Bias generator for CML divider. For TI purposes only.
Control bits for Bias generator for CML divider. For TI purposes only.
Enable for TX clock out from SERDES REFCLK MUX. For TI purposes
only.
Enable for RX clock out from SERDES REFCLK MUX. For TI purposes
only.
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Product Folder Link(s):
SLLS838F – MAY 2007 – REVISED DECEMBER 2009
DEFAULT: 0x30C4
DESCRIPTION
(1)
DEFAULT: 0x0000
DESCRIPTION
DEFAULT: 0x0000
DESCRIPTION
DEFAULT:0x0000
DESCRIPTION
TLK3134
TLK3134
ACCESS
RW
ACCESS
RW
ACCESS
RW
ACCESS
RW
Detailed Description
81

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