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3.4
PRBS Test Generation and Verification Procedures
Use one of the following procedures to generate and verify the respective PRBS test patterns. It is
assumed that an appropriate external cable has been connected between serial outputs and serial inputs.
No functional parallel side connections are necessary.
7
•
1000Base-X 2
– Device Pin Setting(s):
•
Ensure ST primary input pin is high.
•
Ensure CODE primary input pin is low.
– Reset Device:
•
Issue a hard or soft reset (RST_N asserted –or- Write 1 to 0.15)
– Select single ended or differential REFCLK input:
•
If Single Ended REFCLK used - Write 2'b01 to 4/5.37120.15:14
•
If Differential REFCLK used – Write 2'b00 to 4/5.37120.15:14
– Select SERDES TX Reference Clock Input:
•
If Single Ended REFCLK used - Write 2'b10 to 4/5.37120.11:10
•
If Differential REFCLK used – Write 2'b11 to 4/5.37120.11:10
– Select SERDES RX Reference Clock Input:
•
If Single Ended REFCLK used - Write 2'b10 to 4/5.37120.9:8
•
If Differential REFCLK used – Write 2'b11 to 4/5.37120.9:8
– Ensure a legal reference clock operation frequency is selected based on Appendix A, and provision
control settings accordingly. It is also possible to use the Jitter Cleaner during these tests, and the
user should consult Appendix A for further Jitter Cleaner provisioning details.
– Issue Datapath Reset:
•
Write 1'b1 to 16.11
•
Write 1'b0, 1'b1, followed by 1'b0 to 37636.14.
– Enable PRBS Generator (On Channel Desired):
•
Write 1'b1 to 16.6
– Enable Test Pattern Verification:
•
Write 1'b1 to 16.7
– Clear Counters:
•
Read 29.15:0 and discard the value.
– The pattern verification is now in progress.
– Verify Error Free Operation (as many times as desired during the duration of the test period):
•
Read 29.15:0, and verify 16'h0000 is read to confirm error free operation.
– GPO3 contains a real time output that when high indicates if the input PRBS pattern on TD × 3/RD
× 3 is errored.
– GPO2 contains a real time output that when high indicates if the input PRBS pattern on TD × 2/RD
× 2 is errored.
– GPO1 contains a real time output that when high indicates if the input PRBS pattern on TD × 1/RD
× 1 is errored.
– GPO0 contains a real time output that when high indicates if the input PRBS pattern on TD × 0/RD
× 0 is errored.
7
23
•
2
-1/2
-1 PRBS Pin Based Testing
– Device Pin Setting(s):
•
Ensure PRBS_EN primary input pin is high.
•
PRBS Selection:
– For PRBS 2
– For PRBS 2
Copyright © 2007–2009, Texas Instruments Incorporated
-1 PRBS Register Based Testing
7
-1- Ensure ST primary input pin is high.
23
-1- Ensure ST primary input pin is low.
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Product Folder Link(s):
SLLS838F – MAY 2007 – REVISED DECEMBER 2009
Device Reset Requirements/Procedure
TLK3134
TLK3134
101
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