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SIGNAL
DVDD
N10, N12, N17, N6, N8
VDDO
VDDM
A12, A15, A2, A5, A9
VDDQ
VREF1, VREF2
G10, G11, G15, G5, G7, G8, G9
DGND
K10, K11, K12, K14, K7, K8, K9
L10, L11, L17, L7, L8, L9
M10, M11, M13, M4, M7, M8, M9
AVDD
P10, P12, P13 , P4, P5,P6, P8
AGND
VDDR
VDDT
VDDD
Copyright © 2007–2009, Texas Instruments Incorporated
Table 3-7. Voltage Supply and Reference Pins
LOCATION
F11, F6, F8, F9,
G12, G6,
J12, J7
M12
T2
L2
N9
P14, P16, P3
R1
T17
B15, B17, B5
C1, C7, C8
D1
E14, E4
F10, F17, F3, F7
G1, G14
H13, H17, H3, H6
J16
K16
L12
M15
H14
A14
A1, A17, A7
B10
C13, C3
D16, D6
E9
F12, F2
H10, H11, H12,
H7, H8, H9
J10, J11, J8, J9
P2
T15
U17
N11, N7
R11, R14, R5, R8
U12, U6, U9
T11, T14, T3, T5, T8
P9
P11, P7
T4, T9
T10, T13, T7
U15, U3
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SLLS838F – MAY 2007 – REVISED DECEMBER 2009
TYPE
P
Digital Core Power Supply (1.2 V ±5%)
P
LVCMOS and Bias Power (2.5 V ±5%)
P
MDIO Power (2.5 V or 1.2 V ±5%)
XGMII HSTL Power (1.5/1.8 V)
P
1.5 V Operation Range: 1.4 V → 1.6 V
1.8 V Operation Range: 1.7V → 1.9 V
XGMII HSTL Reference Voltage (.75 V or .9 V)
P
These signals should be equal to VDDQ divided by 2.
G
Digital Ground
P
Analog Power (1.2 V ±5%)
G
Analog Ground
P
SERDES Voltage Regulator Input (1.5 V –or– 1.8 V)
P
SERDES Termination Voltage (1.2 V)
P
SERDES Digital Power (1.2 V)
Device Reset Requirements/Procedure
TLK3134
TLK3134
DESCRIPTION
109
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