2.7.27 Parallel To Serial; 2.7.28 Serial To Parallel; 2.7.29 High Speed Cml Output; Clock Tolerance Compensation: Drop - Texas Instruments TLK3134 Data Manual

www.ti.com
RDP/N0
RDP/N1
Input
RDP/N2
RDP/N3
RXD(7:0)
RXD(15:8)
Output
RXD(23:16)
RXD(31:24)
S = Start of Packet, D = Data, T = End of Packet, A = K28.3,
K = K28.5, R = K28.0, I = Idle

2.7.27 Parallel to Serial

The parallel-to-serial shift register on each channel takes in data and converts it to a serial stream. The
shift register is clocked by the internally generated bit clock, which is 10 times the reference clock
(REFCLKP/REFCLKN) frequency. The least significant bit (LSB) for each channel is transmitted first.

2.7.28 Serial to Parallel

For each channel, serial data is received on the RDPx/RDNx pins. The interpolator and clock recovery
circuit will lock to the data stream if the clock to be recovered is within ±200 PPM of the internally
generated bit rate clock. The recovered clock is used to retime the input data stream. The serial data is
then clocked into the serial-to-parallel shift registers. If enabled, the 10-bit wide parallel data is then fed
into 8b/10b decoders.

2.7.29 High Speed CML Output

The high speed data output driver is implemented using Current Mode Logic (CML) with integrated pull up
resistors requires no external components. The line can be directly coupled or AC coupled. Under many
circumstances, AC coupling is desirable.
Copyright © 2007–2009, Texas Instruments Incorporated
Packet
K R S D D D D
K R D D D D D
K R D D D D D
K R D D D D D
I I S D D D D
I I D D D D D
I I D D D D D
I I D D D D D
Figure 2-29. Clock Tolerance Compensation: Drop
Submit Documentation Feedback
Product Folder Link(s):
SLLS838F – MAY 2007 – REVISED DECEMBER 2009
... D D D D A
... D D D T A
... D D D K A
... D D D K A
... D D D D I
... D D D T I
... D D D I I
... D D D I I
TLK3134
TLK3134
IPG
R R K S D
R R K D D
R R K D D
R R K D D
Dropped Column
I I S D D
I I D D D
I I D D D
I I D D D
Detailed Description 45