Hstl Output Switching Characteristics (Sdr Timing Mode Only); Hstl (Sdr Timing Mode Only) Rising Edge Aligned Output Timing Requirements; Hstl (Sdr Timing Mode Only) Falling Edge Aligned Output Timing Requirements - Texas Instruments TLK3134 Data Manual

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4.13 HSTL Output Switching Characteristics (SDR Timing Mode Only)

over operating free-air temperature range (unless otherwise noted)
PARAMETER
T RXCLK Duty Cycle
duty
t RXCLK Period
period
T RXCLK Frequency
freq
T RXCLK rising to RXDATA valid.
pd
T RXCLK falling to RXDATA valid.
pd
RXCLK
V
OH(ac)
RXDATA VDDQ/2
V
OL(ac)
Figure 4-7. HSTL (SDR Timing Mode Only) Rising Edge Aligned Output Timing Requirements
RXCLK
V
OH(ac)
VDDQ/2
RXDATA
V
OL(ac)
Figure 4-8. HSTL (SDR Timing Mode Only) Falling Edge Aligned Output Timing Requirements
Copyright © 2007–2009, Texas Instruments Incorporated
TEST CONDITIONS
Rising and Falling Edge Aligned Data
Note: C = 10pF, using timing reference of VDDQ/2.
load
Rising and Falling Edge Aligned Data
Rising and Falling Edge Aligned Data
Rising Edge Aligned
Note: C = 10pF, using timing reference of VDDQ/2.
load
Falling Edge Aligned
Note: C = 10pF, using timing reference of VDDQ/2.
load
t
PERIOD
t
PERIOD
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SLLS838F – MAY 2007 – REVISED DECEMBER 2009
T
PD
T
PD
TLK3134
TLK3134
MIN MAX UNIT
40% 60%
2.67 16.67 ns
60 375 MHz
–0.10 × +0.10 ×
ps
t t
period period
–0.10 × +0.10 ×
ps
t t
period period
V
OH(ac)
VDDQ/2
V
OL(ac)
V
OH(ac)
VDDQ/2
V
OL(ac)
Electrical Specifications 121