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TLK3134
SLLS838F – MAY 2007 – REVISED DECEMBER 2009
ADDRESS: 0x9301
BIT(s)
NAME
4/5.37633.15:14 HSTL_SLEW_RATE_3 [1:0] 01 = 33% slew control
4/5.37633.11:10 HSTL_SLEW_RATE_2 [1:0] 01 = 33% slew control
4/5.37633.7:6
HSTL_SLEW_RATE_1 [1:0] 01 = 33% slew control
4/5.37633.3:2
HSTL_SLEW_RATE_0 [1:0] 01 = 33% slew control
ADDRESS: 0x9302
BIT(s)
NAME
4/5.37634.15
I_FORCE_UP_N
4/5.37634.14
I_FORCE_UP_P
4/5.37634.13
I_FORCE_DOWN_N
4/5.37634.12
I_FORCE_DOWN_P
4/5.37634.11:9
I_VTP_DRIVE[2:0]
4/5.37634.7:5
I_FILTER_CONTROL[2:0]
4/5.37634.3
I_LOCK
84
Detailed Description
Table 2-142. HSTL_OUTPUT_SLEWRATE_CONTROL
Slew Rate setting for output HSTL cells (for CH 3)
00 = No slew control (fastest edge)
10 = 66 % slew control termination strength
11 = Full slew control (slowest edge)
Slew Rate setting for output HSTL cells (for CH 2)
00 = No slew control (fastest edge)
10 = 66 % slew control termination strength
11 = Full slew control (slowest edge)
Slew Rate setting for output HSTL cells (for CH 1)
00 = No slew control (fastest edge)
10 = 66 % slew control termination strength
11 = Full slew control (slowest edge)
Slew Rate setting for output HSTL cells (for CH 0)
00 = No slew control (fastest edge)
10 = 66 % slew control termination strength
11 = Full slew control (slowest edge)
Table 2-143. HSTL_INPUT_VTP_CONTROL
When set, increases NFET strength in all HSTL input cells. For TI
purposes Only
When set, increases PFET strength in all HSTL input cells. For TI
purposes Only
When set, decreases NFET strength in all HSTL input cells. For TI
purposes Only
When set, decreases PFET strength in all HSTL input cells. For TI
purposes Only
Drive strength control for HSTL input cells
3'b000 = 30 % drive strength increase
3'b001 = 20% drive strength increase
3'b010 = 10% drive strength increase
3'b011 = Normal drive strength (default)
3'b100 = 10% drive strength decrease
3'b101 = 20% drive strength decrease
3'b110 = 30% drive strength decrease
3'b111 = 40% drive strength decrease
Filter Control
3'b000 = Impedance change filtering off
3'b001 = Update on 2 consecutive update requests
3'b010 = Update on 3 consecutive update requests(default)
3'b011 = Update on 4 consecutive update requests
3'b100 = Update on 5 consecutive update requests
3'b101 = Update on 6 consecutive update requests
3'b110 = Update on 7 consecutive update requests
3'b111 = Update on 8 consecutive update requests
Impedance Lock Control
When set, disables dynamic impedance control updates for HSTL input
cells
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DESCRIPTION
DEFAULT: 0x0640
DESCRIPTION
Copyright © 2007–2009, Texas Instruments Incorporated
TLK3134
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