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SIGNAL
LOCATION
CODE
M3
SIGNAL
LOCATION
VOLTAGE
TDI
N13
TDO
R15
TMS
P15
TCK
P17
TRST_N
N15
SIGNAL
LOCATION
VOLTAGE
MDC
T16
MDIO
U16
PRTAD[4:
N5, N4, N3,
0]
N2, T1
Copyright © 2007–2009, Texas Instruments Incorporated
Table 3-1. Global Signals (continued)
VOLTAGE
TYPE
2.5 V LVCMOS
VDDO
Input
Table 3-2. JTAG Signals
TYPE
2.5 V LVCMOS
JTAG Input Data. TDI is used to serially shift test data and test instructions
VDDO
Input (Internal
into the device during the operation of the test port.
Pullup)
JTAG Output Data. TDO is used to serially shift test data and test instructions
2.5 V LVCMOS
VDDO
out of the device during operation of the test port. When the JTAG port is not
Output
in use, TDO is in a high impedance state.
2.5 V LVCMOS
JTAG Mode Select. TMS is used to control the state of the internal test-port
VDDO
Input (Internal
controller.
Pullup)
2.5 V LVCMOS
JTAG Clock. TCK is used to clock state information and test data into and out
VDDO
Input
of the device during the operation of the test port.
2.5 V LVCMOS
JTAG Test Reset. TRST_N is used to reset the JTAG logic into system
VDDO
Input (Internal
operational mode.
Pullup)
Table 3-3. MDIO Related Signals
TYPE
1.2 V OR 2.5 V
VDDM
LVCMOS Input
1.2 V OR 2.5 V
VDDM
LVCMOS Input/
Output
2.5 V LVCMOS
VDDO
Input
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Product Folder Link(s):
Code Enable. This signal selects different functionality based on the
setting of the ST primary chip input pin.
ST=0:
This signal is logically OR'd with the XAUI_ORDER register bit (Register
Bit 32809.15). XAUI applications can either tie this input signal high
(preferred) or tie this signal low (must program the XAUI_ORDER register
bit after device reset to high if CODE is tied off low). 10GFC applications
must tie this signal low.
ST=1:
This signal is logically OR'd with the PCS_EN register bit (Register Bit
17.3). RGMII/GMII applications can either tie this input signal high
(preferred) or tie this signal low (must program the PCS_EN 17.3 register
bit after device reset to high if CODE is tied off low). Non RGMII/GMII
applications must tie this input signal low.
Management Interface Clock This clock is used to sample the MDIO signal.
Management Interface Data This bidirectional data line for MDIO Port is
sampled on the rising edge of MDC.
THIS SIGNAL MUST BE EXTERNALLY PULLED UP TO VDDM. Consult
IEEE802.3 Clause 22/45 for an appropriate resistance value.
Port Address Used to select the Device Id/Port ID in Clause 22/Clause 45
MDIO modes.
ST=0 (Clause 45 Mode):
If PRTAD[0] is a 0, then a PHY device is selected for XAUI/10GFC register
accesses (4.xxxxx.x).
If PRTAD[0] is a 1, then a DTE device is selected for XAUI/10GFC register
accesses (5.xxxxx.x).
PRTAD[4:1] selects the Clause 45 port address (TLK3134 must be located
on even boundaries since the lowest port address bit determines DTE/PHY,
and is used as a device address instead of port address).
ST=1 (Clause 22 Mode):
PRTAD[4:2] selects a block of four sequential Clause 22 port addresses.
Each channel is implemented as a different port address, and can be
accessed by setting the appropriate port address field within the Clause 22
MDIO transaction. PRTAD[1:0] pins are not used in Clause 22 mode.
Channel 0 responds to port address 0 within the block of four port addresses.
Channel 1 responds to port address 1 within the block of four port addresses.
Channel 2 responds to port address 2 within the block of four port addresses.
Channel 3 responds to port address 3 within the block of four port addresses.
TLK3134
SLLS838F – MAY 2007 – REVISED DECEMBER 2009
DESCRIPTION
DESCRIPTION
DESCRIPTION
Device Reset Requirements/Procedure
TLK3134
105
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