Rx_Ctc_Delete_Count; Data_Down; Rx_Mode_Control; Clock_Down_Status - Texas Instruments TLK3134 Data Manual

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ADDRESS: 0x801C
BIT(s) NAME
4/5.32796.15:0 Idle delete count
ADDRESS: 0x801D
BIT(s) NAME
4/5.32797.3 Lane 3 data down
4/5.32797.2 Lane 2 data down
4/5.32797.1 Lane 1 data down
4/5.32797.0 Lane 0 data down
ADDRESS: 0x801E
BIT(s)
4/5.32798.15 RX CTC disable
4/5.32798.14 IPG Checker bypass
4/5.32798.11 Lane 3 8B/10B decoder bypass
4/5.32798.10 Lane 2 8B/10B decoder bypass
4/5.32798.9 Lane 1 8B/10B decoder bypass
4/5.32798.8 Lane 0 8B/10B decoder bypass
Consider sequence column part
4/5.32798.7
of IPG
4/5.32798.3 RX Lane align bypass enable
ADDRESS: 0x801F
BIT(s)
4/5.32799. 7 Lane 3 clock 312 down
4/5.32799. 6 Lane 2 clock 312 down
4/5.32799. 5 Lane 1 clock 312 down
4/5.32799. 4 Lane 0 clock 312 down
4/5.32799. 3 Lane 3 clock 156 down
4/5.32799. 2 Lane 2 clock 156 down
4/5.32799. 1 Lane 1 clock 156 down
4/5.32799. 0 Lane 0 clock 156 down
ADDRESS: 0x8020
BIT(s)
4/5.32800. 15 XAUI datapath reset
Copyright © 2007–2009, Texas Instruments Incorporated
Table 2-59. RX_CTC_DELETE_COUNT
Counter for number of idle deletions
Table 2-60. DATA_DOWN
When high, indicates that link for the corresponding lane was inactive (data
did not toggle) for 4095 cycles of recovered clock from serial input data
The recovered clock is generated internally by the PLL from the 156Mhz
Reference clock.
Table 2-61. RX_MODE_CONTROL
NAME
When set, disables clock tolerance compensation on the RX
side. (Default 1'b0)
When set, disables the replacement of /A/K/R/ into Idles and
also bypasses end-of-packet error checking. (Default 1'b0)
When set, disables the XAUI 8B/10B decoding for the
corresponding lane. (Default 1'b0)
When high, sequence columns are counted as part of IPG.
When low, sequence columns are not counted as IPG (Default
1'b0)
When set, enables lane alignment bypass on the RX side
Table 2-62. CLOCK_DOWN_STATUS
NAME
When high, indicates that serial clock generated by SERDES TX
is down on the corresponding lane for 255 or more cycles. The
detection is done on the transmit side.
When high, indicates that 156MHz XGMII clock is down on the
corresponding lane for 255 or more cycles. The detection is done
on the transmit side
Table 2-63. DATAPATH_RESET_CONTROL
NAME
When set, resets XAUI data path but does not reset any R/W registers.
(Default 1'b0)
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SLLS838F – MAY 2007 – REVISED DECEMBER 2009
DEFAULT: 0xFFFD
DESCRIPTION
DEFAULT: 0x0000
DESCRIPTION
DEFAULT: 0x0000
DESCRIPTION
DEFAULT: 0x0000
DESCRIPTION
DEFAULT: 0x0000
DESCRIPTION
TLK3134
TLK3134
ACCESS
RO/COR
ACCESS
RO/COR
ACCESS
RW
RW
RW
RW
RW
ACCESS
RO/LH
RO/LH
ACCESS
RW/SC
Detailed Description 59