Texas Instruments TLK3134 XAUI Manuals

Manuals and User Guides for Texas Instruments TLK3134 XAUI. We have 2 Texas Instruments TLK3134 XAUI manuals available for free PDF download: Data Manual, User Manual

Texas Instruments TLK3134 XAUI Data Manual (151 pages)

4-Channel Multi-Rate Transceiver

Brand: Texas Instruments | Category: Transceiver | Size: 1.68 MB

Table of Contents
2
1 Introduction

11
- Features
  11
- Applications
  11
- Pin out
  12
- Description
  12
- System Block Diagram - XAUI
  13
2 Detailed Description

14
- Clocking Modes
  14
- System Block Diagram - XAUI Backplane
  14
- Block Diagram - TLK3134 Clocking Architecture
  14
  - Operating Frequency Range
    15
  - CPRI Latency Support
    15
  - Powerdown Mode
    15
  - Application Examples
    15
- Supported Protocol Rates and REFCLK Values
  15
- Quad 10-Bit SERDES Application
  16
- XAUI Mode - XAUI (Serial) Loopback Application
  16
- XAUI Mode - XGMII (Parallel ) Loopback Application
  16
- Custom Independent Configuration Application
  17
- TLK3134 Block Diagram
  18
- Detailed Xaui/1000Base-X Core Block Diagram
  19
- Block Diagram of SERDES Core
  19
  - Device Operation Modes
    20
  - Parallel Interface Modes - Detailed Description
    21
    
    2.7.1 XAUI/10GFC Mode
    21
- XAUI - Lane to Functional Pin Mapping (XAUI_ORDER = 1)
  21
- 10GFC - Lane to Functional Pin Mapping (XAUI_ORDER = 0)
  21
  - RGMII Mode (Reduced Gigabit Media Independent Interface)
    22
- RGMII - Individual Channel Byte Ordering - Channel 0 Example
  22
- RGMII - Lane to Functional Pin Mapping
  22
  - RTBI Mode (Reduced Ten Bit Interface)
    23
- RTBI - Individual Channel Byte Ordering - Channel 0 Example
  23
- RTBI - Lane to Functional Pin Mapping
  23
  - TBI Mode (Ten Bit Interface)
    24
- TBI - Individual Channel Byte Ordering - Channel 0 Example
  24
- TBI - Lane to Functional Pin Mapping
  24
  - GMII Mode (Gigabit Media Independent Interface)
    25
- GMII - Individual Channel Byte Ordering - Channel 0 Example
  25
- GMII - Lane to Functional Pin Mapping
  25
  - EBI Mode (Eight Bit Interface)
    26
- EBI - Individual Channel Byte Ordering - Channel 0 Example
  26
- EBI - Lane to Functional Pin Mapping
  26
  - REBI Mode (Reduced Eight Bit Interface)
    27
- REBI - Individual Channel Byte Ordering - Channel 0 Example
  27
- REBI - Lane to Functional Pin Mapping
  27
  - NBI Mode (Nine Bit Interface Mode)
    28
- NBI - Individual Channel Byte Ordering - Channel 0 Example
  28
- NBI - Lane to Functional Pin Mapping
  28
  - RNBI Mode (Reduced Nine Bit Interface)
    29
- RNBI - Individual Channel Byte Ordering - Channel 0 Example
  29
- RNBI - Lane to Functional Pin Mapping
  29
  - TBID Mode (Ten Bit Interface DDR)
    30
- TBID - Individual Channel Byte Ordering - Channel 0 Example
  30
- TBID - Lane to Functional Pin Mapping
  30
  - NBID Mode (Nine Bit Interface DDR)
    31
- NBID - Individual Channel Byte Ordering - Channel 0 Example
  31
- NBID - Lane to Functional Pin Mapping
  31
  - 2.7.12 Parallel Interface Clocking Modes
    32
- Receive Interface Timing - Source Centered/Aligned
  32
  - 2.7.13 Parallel Interface Data
    33
  - 2.7.14 Transmission Latency
    33
- Transmit Interface Timing
  33
- Transmission Latency
  34
- Receiver Latency
  34
- Valid K-Codes
  35
- Valid XGMII Channel Encodings
  35
  - 2.7.18 Comma Detect and 8B/10B Decoding
    36
  - 2.7.19 Channel Initialization and Synchronization
    36
- Receive Data Controls
  36
  - 2.7.20 Channel State Descriptions
    37
- Channel Synchronization State Machine
  37
- Column De-Skew State Machine
  39
  - 2.7.24 Column State Descriptions
    40
  - 2.7.25 Inter-Packet Gap Management
    41
- Channel Deskew Using Alignment Code
  41
- Inter-Packet Gap Management
  42
- IPG Management State Machine
  43
- IPG Management State Machine Notation
  43
  - Clock Tolerance Compensation (CTC)
    44
- Clock Tolerance Compensation: Add
  44
- Clock Tolerance Compensation: Drop
  45
- Example High Speed I/O AC Coupled Mode
  46
  - 2.7.30 High Speed Receiver
    47
  - 2.7.31 Loopback
    47
  - 2.7.32 Link Test Functions
    47
  - 2.7.33 MDIO Management Interface
    47
- Output Differential Voltage with 1-Tap FIR De-Emphasis
  47
  - 2.7.34 MDIO Protocol Timing
    48
- CL45 - Management Interface Extended Space Address Timing
  48
- CL45 - Management Interface Extended Space Write Timing
  48
  - 2.7.35 Clause 22 Indirect Addressing
    49
- CL45 - Management Interface Extended Space Read Timing
  49
- CL45 - Management Interface Extended Space Read and Increment Timing
  49
- CL22 - Management Interface Read Timing
  49
- CL22 - Management Interface Write Timing
  49
- CL22 - Indirect Address Method - Address Write
  50
- CL22 - Indirect Address Method - Data Write
  50
- CL22 - Indirect Address Method - Data Read
  50
  - Programmers Reference
    51
    
    XAUI Programmers Reference (ST = 0)
    51
- Xs_Control_1
  51
- Xs_Status_1
  51
- Xs_Device_Identifier_1
  51
- Xs_Device_Identifier_2
  51
- Xs_Speed_Ability
  52
- Xs_Devices_In_Package_1
  52
- Xs_Devices_In_Package_2
  52
- Xs_Status_2
  52
- Xs_Package_Identifier_1
  52
- Xs_Package_Identifier_2
  53
- Xs_Lane_Status
  53
- Xs_Test_Control
  53
- Test_Config
  53
- Test_Verification_Control
  53
- Tx_Fifo_Status
  54
- Tx_Fifo_Drop_Count
  54
- Tx_Fifo_Insert_Count
  54
- Tx_Codegen_Status
  54
- Lane_0_Test_Error_Count
  54
- Lane_1_ Test_Error_Count
  55
- Lane_2_ Test_Error_Count
  55
- Lane_3_ Test_Error_Count
  55
- 10Gfccjpat_Crpat_Cjpat_Test_Error_Count_1
  55
- 10Gfccjpat_Crpat_Cjpat_Test_Error_Count_2
  55
- Lane_0_Eop_Error_Count
  55
- Lane_1_Eop_Error_Count
  55
- Lane_2_Eop_Error_Count
  55
- Lane_3_Eop_Error_Count
  55
- Lane_0_Code_Error_Count
  56
- Lane_1_Code_Error_Count
  56
- Lane_2_Code_Error_Count
  57
- Lane_3_Code_Error_Count
  57
- Rx_Channel_Sync_State
  57
- Rx_Lane_Align_Status
  57
- Rx_Channel_Sync_Status
  57
- Bit_Order
  57
- Loopback_Control
  58
- Tx_Mode_Control
  58
- Rx_Ctc_Status
  58
- Rx_Ctc_Insert_Count
  58
- Rx_Ctc_Delete_Count
  59
- Data_Down
  59
- Rx_Mode_Control
  59
- Clock_Down_Status
  59
- Datapath_Reset_Control
  59
- Test_Pattern_Status
  60
- Lane_0_Error_Code
  60
- Lane_1_Error_Code
  60
- Lane_2_Error_Code
  60
- Lane_3_Error_Code
  60
- Rx_Phase_Shift_Control
  60
- Channel_Sync_Control
  61
- Xgmii_Io_Mode_Control
  61
- 10G_Mode_Control
  61
- Rx_Clk_Output_Control
  61
  - Programmers Reference
    62
- Phy_Control_1
  62
- Phy_Status_1
  63
- Phy_Identifier_1
  63
- Phy_Identifier_2
  63
- Phy_Ext_Status
  63
- Phy_Ch_Control_1
  64
- Phy_Ch_Control_2
  64
- Phy_Rx_Ctc_Fifo_Status
  66
- Phy_Tx_Ctc_Fifo_Status
  66
- Phy_Tx_Wide_Fifo
  66
- Phy_Test_Pattern_Sync_Status
  66
- Phy_Test_Pattern_Counter
  66
- Phy_Crpat_Pattern_Counter_1
  66
- Phy_Crpat_Pattern_Counter_2
  67
- Phy_Test_Mode_Control
  67
- Phy_Channel_Status
  67
- Phy_Prbs_High_Speed_Test_Counter
  67
- Phy_Ext_Address_Control
  67
- Phy_Ext_Address_Data
  67
  - 2.10 Top Level Programmers Reference
    68
- Serdes_Pll_Config
  68
- PLL Multiplier Control
  68
- Serdes_Rate_Config_Tx_Rx
  68
- Serdes_Rx0_Config
  70
- Serdes_Rx1_Config
  70
- Serdes_Rx2_Config
  71
- Serdes_Rx3_Config
  71
- Serdes_Tx0_Config
  72
- Serdes_Tx1_Config
  72
- Serdes_Tx2_Config
  73
- Serdes_Tx3_Config
  73
- Transmit De-Emphasis Control
  74
- Output Swing Control
  74
- Serdes_Test_Config_Tx
  74
- Serdes_Test_Config_Rx
  76
- Serdes_Rx0_Status
  76
- Serdes_Rx1_Status
  76
- Serdes_Rx2_Status
  77
- Serdes_Rx3_Status
  77
- Serdes_Tx0_Status
  77
- Serdes_Tx1_Status
  77
- Serdes_Tx2_Status
  77
- Serdes_Tx3_Status
  78
- Serdes_Pll_Status
  78
- Jc_Clock_Mux_Control
  78
- Jc_Vtp_Clk_Div_Control
  79
- Jc_Delay_Stopwatch_Clk_Div_Control
  79
- Jc_Delay_Stopwatch_Counter
  79
- Jc_Refclk_Fb_Div_Control
  79
- Jc_Rxb_Output_Clk_Div_Control
  80
- Jc_Charge_Pump_ Control
  80
- Charge Pump Control Setting (CP_CTRL)
  80
- Jc_Pll_Control
  81
- Jc_Test_Control_1
  81
- Jc_Test_Control_2
  81
- Jc_Ti_Test_Control_1
  81
- Jc_Ti_Test_Control_2
  82
- Jc_Trim_Status
  82
- Die_Id_7
  82
- Die_Id_6
  82
- Die_Id_5
  82
- Die_Id_4
  82
- Die_Id_3
  82
- Die_Id_2
  82
- Die_Id_1
  83
- Die_Id_0
  83
- Efuse_Status
  83
- Hstl_Input_Termination_Control
  83
- Hstl_Output_Slewrate_Control
  84
- Hstl_Input_Vtp_Control
  84
- Hstl_Output_Vtp_Control
  85
- Hstl_Global_Control
  85
- Tx0_Dll_Control
  86
- Tx1_Dll_Control
  86
- Tx2_Dll_Control
  86
- Tx3_Dll_Control
  86
- Rx0_Dll_Control
  87
- Rx1_Dll_Control
  87
- Rx2_Dll_Control
  87
- Rx3_Dll_Control
  87
- DLL Offset Control
  87
- Tx0_Dll_Status
  88
- Tx1_Dll_Status
  88
- Tx2_Dll_Status
  88
- Tx3_Dll_Status
  88
- Rx0_Dll_Status
  88
- Rx1_Dll_Status
  88
- Rx2_Dll_Status
  88
- Rx3_Dll_Status
  89
- Ch0_Testfail_Err_Counter
  89
- Ch1_Testfail_Err_Counter
  89
- Ch2_Testfail_Err_Counter
  89
- Ch3_Testfail_Err_Counter
  89
- Stci_Control_Status
  89
- Testclk_Control
  90
- Bidi_Cmos_Control
  90
- Debug_Control
  90
- Duty_Cycle_Control
  90
3 Device Reset Requirements/Procedure

91
- Xaui Mode (Xgmii)
  91
- Gigabit Ethernet Mode (RGMII)
  94
- Jitter Test Pattern Generation and Verification Procedures
  97
- PRBS Test Generation and Verification Procedures
  101
- Signal Pin Description
  104
- Global Signals
  104
- JTAG Signals
  105
- MDIO Related Signals
  105
- Parallel Data Pins
  106
- Efuse_Control
  108
- Serial Side Data/Clock Pins
  108
- Miscellaneous Pins
  108
- Voltage Supply and Reference Pins
  109
- Jitter Cleaner Related Pins
  110
- Device Pinout Diagram - Part 1 (Top View)
  111
- Device Pinout Diagram - Part 2 (Top View)
  111
4 Electrical Specifications

112
APPENDIX A - Frequency Ranges Supported

129
APPENDIX B - Jitter Cleaner PLL External Loop Filter

146
- Jitter Cleaner External Loop Filter
  146
APPENDIX C - Device Test Mode

147
- Device Mode Configuration
  147
- Device Test Mode Pin Configuration
  147
- Important Notice
  151

Texas Instruments TLK3134 XAUI User Manual (62 pages)

Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module

Brand: Texas Instruments | Category: Motherboard | Size: 4.24 MB

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Texas Instruments TLK3134 XAUI Manuals

Texas Instruments TLK3134 XAUI Data Manual (151 pages)

Table of Contents

1 Introduction

2 Detailed Description

3 Device Reset Requirements/Procedure

4 Electrical Specifications

APPENDIX A - Frequency Ranges Supported

APPENDIX B - Jitter Cleaner PLL External Loop Filter

APPENDIX C - Device Test Mode

Texas Instruments TLK3134 XAUI User Manual (62 pages)

Table of Contents

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