Texas Instruments CC1020 Manual
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Texas Instruments CC1020 Manual

Low-power rf transceiver for narrowband systems
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CC1020 Low-Power RF Transceiver for Narrowband Systems
1 Device Overview
1.1

Features

1
• True Single Chip UHF RF Transceiver
• Frequency Range 402 MHz to 470 MHz
and 804 MHz to 960 MHz
• High Sensitivity
– Up to –118 dBm for a 12.5 kHz Channel
• Programmable Output Power
• Low Current Consumption
– RX: 19.9 mA
• Low Supply Voltage
– 2.3 V to 3.6 V
• No External IF Filter Needed
• Low-IF Receiver
• Very Few External Components Required
• Small Size
– QFN 32 Package
1.2

Applications

•
Narrowband Low-Power UHF Wireless Data
Transmitters and Receivers With Channel
Spacing as Low as 12.5 and 25 kHz
•
402-, 424-, 426-, 429-, 433-, 447-, 449-, 469-,
868-, 915-, 960-MHz ISM/SRD Band Systems
1.3

Description

CC1020 is a true single-chip UHF transceiver designed for very low-power and very low-voltage wireless
applications. The circuit is mainly intended for the ISM (Industrial, Scientific, and Medical) and SRD (Short
Range Device) frequency bands at 402-, 424-, 426-, 429-, 433-, 447-, 449-, 469-, 868-, 915-, and 960-
MHz, but can easily be programmed for multichannel operation at other frequencies in the 402- to 470-
MHz and 804- to 960-MHz range.
The CC1020 device is especially suited for narrow-band systems with channel spacing of 12.5 or 25 kHz
complying with ARIB STD-T67 and EN 300 220.
The main operating parameters of the CC1020 device can be programmed with a serial bus, thus making
CC1020 a very flexible and easy-to-use transceiver.
In a typical system, the CC1020 device will be used together with a microcontroller and a few external
passive components.
TI recommends using the latest RF performance line device CC1120 as successor of CC1020:
www.ti.com/rfperformanceline
PART NUMBER
CC1020
(1) For more information, see
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Sample &
Product
Buy
Folder
Table 1-1. Device Information
Section
8, Mechanical Packaging and Orderable Information.
Tools &
Technical
Software
Documents
SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015
• Pb-Free Package
• Digital RSSI and Carrier Sense Indicator
• Data Rate up to 153.6 kBaud
• OOK, FSK, and GFSK Data Modulation
• Integrated Bit Synchronizer
• Image Rejection Mixer
• Programmable Frequency and AFC Make Crystal
Temperature Drift Compensation Possible Without
TCXO
• Suitable for Frequency Hopping Systems
• Suited for Systems Targeting Compliance With
EN 300 220, FCC CFR47 Part 15, ARIB STD-T67,
and ARIB STD-T96
• Development Kit Available
• Easy-to-Use Software for Generating the CC1020
Configuration Data
•
AMR – Automatic Meter Reading
•
Wireless Alarm and Security Systems
•
Home Automation
•
Low Power Telemetry
(1)
PACKAGE
VQFNP (32)
Support &
Community
BODY SIZE (NOM)
7.00 mm × 7.00 mm
CC1020

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Summary of Contents for Texas Instruments CC1020

  • Page 1: Features

    The main operating parameters of the CC1020 device can be programmed with a serial bus, thus making CC1020 a very flexible and easy-to-use transceiver. In a typical system, the CC1020 device will be used together with a microcontroller and a few external passive components.

  • Page 2: Device Overview

    CC1020 SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015 www.ti.com Functional Block Diagram Figure 1-1 shows the system block diagram of the CC1020 device. DIGITAL DEMODULATOR - Digital RSSI RF_IN LNA 2 - Gain Control - Image Suppression - Channel Filtering...

  • Page 3: Table Of Contents

    Configuration Overview ..........Glossary ......Microcontroller Interface Mechanical Packaging and Orderable .............. 4-wire Serial Configuration Interface Information ..............Signal Interface Packaging Information Table of Contents Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...

  • Page 4: Revision History

    Changed Register table format to new TI standards. Changes from January 19, 2015 to February 19, 2015 Page ....................• Updated RUZ package to RSS. Revision History Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...

  • Page 5: Terminal Configuration And Functions

    SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015 3 Terminal Configuration and Functions Pin Diagram Figure 3-1 shows pin names and locations for the CC1020 device. The CC1020 comes in a QFN 32-type package. 32 31 30 29 28 27 26 25 PCLK 1...
  • Page 6 Power supply connection (3 V typical) for digital modules Programming chip select, active low, for configuration interface. Internal PSEL Digital input pullup resistor. Terminal Configuration and Functions Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...

  • Page 7: Specifications

    The same supply voltage should be used for digital (DVDD) and analog (AVDD) power. Supply voltage A 3.0 ±0.1 V supply is recommended to meet the ARIB STD-T67 selectivity and output power tolerance requirements. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...

  • Page 8: Rf Transmit

    Output power +10/+5 dBm at 433/868 MHz under any 868 MHz –20 to +5 operating conditions (refer to CC1020 Errata Note 003 in the CC1020 product folder). See Section 5.11 for details.

  • Page 9: Rf Receive

    BER = 10 The receiver channel filter 6 dB System noise bandwidth is programmable from 9.6 to 307.2 bandwidth 9.6 kHz to 307.2 kHz. See Section 5.9.2. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 10 Signal level for BER = 10 102.4 kHz channel filter bandwidth. (1) Two tone test (+10 MHz and +20 MHz) (2) Close-in spurious response rejection. (3) Out-of-band spurious response rejection. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 11 NRZ mode Baud Time from clocking the data on the Data latency transmitter DIO pin until data is Manchester mode Baud available on receiver DIO pin. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...

  • Page 12: Rssi / Carrier Sense

    9.6 kHz to 307.2 kHz. See Section 5.9.2 for details. At 2.4 kBaud AFC resolution Given as Baud rate / 16. See Section 5.9.3 details. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...

  • Page 13: Crystal Oscillator

    (2) Crystal oscillator temperature compensation can be done using the fine step PLL frequency programmability and the AFC feature. See Section 5.9.13 for details. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...

  • Page 14: Frequency Synthesizer

    Depends on loop filter with crystal oscillator component values and PLL_BW register 500 kHz channel spacing µs running. setting. See Table 5-12 for more details. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...

  • Page 15: Digital Inputs And Outputs

    0.93 PA_EN pins 2.5 V on LNA_EN, 0.92 PA_EN pins Sink current 2.0 V on LNA_EN, 0.89 PA_EN pins 1.5 V on LNA_EN, 0.79 PA_EN pins Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...

  • Page 16: Current Consumption

    JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements Power dissipation of 2 W and an ambient temperature of 70ºC is assumed. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...

  • Page 17: Detailed Description

    5-1. Only signal pins are shown. CC1020 features a low-IF receiver. The received RF signal is amplified by the low-noise amplifier (LNA and LNA2) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF, the I/Q signal is complex filtered and amplified, and then digitized by the ADCs.

  • Page 18: Configuration Overview

    These hexadecimal numbers will then be the necessary input to the microcontroller for the configuration of CC1020. In addition, the program will provide the user with the component values needed for the input/output matching circuit, the PLL loop filter and the LC filter.

  • Page 19: Microcontroller Interface

    SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015 Microcontroller Interface Used in a typical system, CC1020 will interface to a microcontroller. This microcontroller must be able to: • Program CC1020 into different modes via the 4-wire serial configuration interface (PDI, PDO, PCLK and PSEL).

  • Page 20: 4-Wire Serial Configuration Interface

    The configuration registers can also be read by the microcontroller via the same configuration interface. The seven address bits are sent first, then the R/W bit set low to initiate the data read-back. CC1020 then returns the data from the addressed register. PDO is used as the data output and must be configured as an input by the microcontroller.

  • Page 21: Signal Interface

    The CC1020 can be used with NRZ (Non-Return-to-Zero) data or Manchester (also known as bi-phase- level) encoded data. CC1020 can also synchronize the data from the demodulator and provide the data clock at DCLK. The data format is controlled by the DATA_FORMAT[1:0] bits in the MODEM register.
  • Page 22 In transmit mode CC1020 provides the data clock at DCLK and DIO is used as data input. Data is clocked into CC1020 at the rising edge of DCLK and should be in NRZ format. The data is modulated at RF with Manchester code.
  • Page 23 Clock provided by CC1020 Clock provided by CC1020 Data provided by CC1020 Data provided by CC1020 Figure 5-7. Synchronous Manchester Encoded Mode (SEP_DI_DO = 0) Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...

  • Page 24: Data Rate Programming

    In asynchronous transparent UART mode any data rate up to 153.6 kBaud can be used. Table 5-2. DIV2 for Different Settings of MCLK_DIV2 MCLK_DIV2[1:0] DIV2 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 25 CRYSTAL FREQUENCY [MHz] DATA RATE [kBaud] 4.9152 7.3728 9.8304 12.288 14.7456 17.2032 19.6608 0.45 4.096 8.192 14.4 16.384 19.2 28.8 32.768 38.4 57.6 65.536 76.8 115.2 153.6 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...

  • Page 26: Frequency Programming

    ´ (10) OOK (On-Off Keying) is used if TXDEV_M[3:0] = 0000. The TX_SHAPING bit in the DEVIATION register controls Gaussian shaping of the modulation signal. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...

  • Page 27: Receiver

    See AN022 CC1020 Crystal Frequency Selection (SWRA070) for more details. For IF frequencies other than 300 to 320 kHz and for high frequency deviation and high data rates (typically ≥...
  • Page 28 [kHz] [kHz] [decimal(binary)] 12.5 12.288 24 (11000b) 19.2 15 (01111b) 25.6 11 (01011b) 51.2 5 (00101b) 102.4 2 (00010b) 153.6 1 (00001b) 307.2 0 (00000b) Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 29 IF frequency. However, if there is some frequency error between the transmitter and the receiver, the bit decision level should be adjusted accordingly. In CC1020, this is done automatically by measuring the two frequencies and use the average value as the decision level.
  • Page 30 Figure 6-1, which includes an external T/R switch. Refer to AN029 CC1020/1021 Automatic Frequency Control (AFC) (SWRA063) for plots of sensitivity versus frequency offset. Table 5-6. Typical Receiver Sensitivity as a Function of Data Rate at 433 MHz, FSK Modulation, –3...
  • Page 31 SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015 5.9.5 RSSI CC1020 has a built-in RSSI (Received Signal Strength Indicator) giving a digital value that can be read form the RSSI register. The RSSI reading must be offset and adjusted for VGA gain setting (VGA_SETTING[4:0] in the VGA3 register).
  • Page 32 10. Write XP-DX to PHASE_COMP register. 11. Wait at least 3 ms. Measure signal strength Y1 as filtered average of 8 reads from RSSI register with Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 33 N. A good starting point is N = 8. As accuracy is more important in the last fine-calibration steps, it can be worthwhile to increase N for each loop iteration. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 34 5.9.8 Linear IF Chain and AGC Settings CC1020 is based on a linear IF chain where the signal amplification is done in an analog VGA (Variable Gain Amplifier). The gain is controlled by the digital part of the IF chain after the ADC (Analog to Digital Converter).
  • Page 35 Zero level depends on front-end settings and VGA_SETTING value. Figure 5-15. Relationship Between RSSI, Carrier Sense Level, and AGC Settings CS_LEVEL, VGA_UP and VGA_DOWN Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 36 4. In general the first bit of sync should be opposite of last bit in preamble, to achieve one more transition. The recommended sync words for CC1020 are 2 bytes (0xD391), 3 bytes (0xD391DA) or 4 bytes (0xD391DA26) and are selected as the best compromise of the above criteria.
  • Page 37 By setting SEQ_PD = 1 in the MAIN register, CC1020 is set in power down mode. If SEQ_PSEL = 1 in the SEQUENCING register the automatic power-up sequence is initiated by a negative transition on the PSEL pin.
  • Page 38 Figure 5-16. Automatic Power-up Sequencing Flow Chart 5.9.13 Automatic Frequency Control CC1020 has a built-in feature called AFC (Automatic Frequency Control) that can be used to compensate for frequency drift. The average frequency offset of the received signal (from the nominal IF frequency) can be read in the AFC register.

  • Page 39: Transmitter

    The TX_SHAPING bit in the DEVIATION register enables the GFSK. GFSK is recommended for narrowband operation. Figure 5-18 Figure 5-19 show typical eye diagrams for 434 MHz and 868 MHz operation, respectively. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 40 Figure 5-20 Figure 5-21. However, the output power can be controlled in finer steps using all the available bits in the PA_POWER register. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 41 The user should therefore add a delay equivalent to at least 2 bits after the data payload has been transmitted before switching off the PA (that is, before stopping the transmission). Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...

  • Page 42: Input And Output Matching And Filtering

    2 bit periods is a good compromise between performance and PA ramping time. 5.11 Input and Output Matching and Filtering When designing the impedance matching network for the CC1020 the circuit must be matched correctly at the harmonic frequencies as well as at the fundamental tone. A recommended matching network is shown Figure 5-22.
  • Page 43 82 Ω, 5%, 0402 82 Ω, 5%, 0402 82 Ω, 5%, 0402 (1) DNM = Do Not Mount Figure 5-23. Typical LNA Input Impedance, 200 to 1000 MHz Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 44 Figure 5-24. Typical Optimum PA Load Impedance, 433 MHz Table 5-9. Impedances at the First 5 Harmonics (433 MHz Matching Network) FREQUENCY REAL IMAGINARY (MHz) (Ohms) (Ohms) 1299 –563 1732 –123 2165 –66 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...

  • Page 45: Frequency Synthesizer

    UHF range (402 to 470 and 804 to 960 MHz). The BANDSELECT bit in the ANALOG register selects the frequency band. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 46 C6 = 100 nF C7 = 3900 pF C8 = 1000 pF R2 = 2.2 kΩ R3 = 6.8 kΩ Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 47 To check that the PLL is in lock the user should monitor the LOCK_CONTINUOUS bit in the STATUS register. The LOCK_CONTINUOUS bit can also be monitored at the LOCK pin, configured by LOCK_SELECT[3:0] = 0010. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 48 There is a small, but finite, possibility that the PLL self-calibration will fail. The calibration routine in the source code should include a loop so that the PLL is re-calibrated until PLL lock is achieved if the PLL does not lock the first time. Refer to CC1020 Errata Note 004, available in the CC1020 product folder.
  • Page 49 The PLL turn-on time depends on the PLL loop filter bandwidth. Table 5-12 gives the PLL turn-on time for different PLL loop filter bandwidths. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 50 Up to 153.6 kBaud data rate, 500 — kHz channel spacing (1) 1) 307.2 kHz step, 2) 1 channel step, 3) 1 MHz step Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...

  • Page 51: Vco And Lna Current Control

    Registers can be programmed freely in any order. The CC1020 should then be calibrated in both RX and TX mode. After this is completed, the CC1020 is ready for use. See the detailed procedure flowcharts in...
  • Page 52 Calibrate VCO and PLL MAIN: PD_MODE=1, FS_PD=1, MAIN: PD_MODE=1, FS_PD=1, XOSC_PD=1, BIAS_PD=1 XOSC_PD=1, BIAS_PD=1 PA_POWER=00h PA_POWER=00h Power Down mode Power Down mode Figure 5-27. Initializing Sequence Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...

  • Page 53: On-Off Keying (Ook)

    “carrier sense” level (programmed as CS_LEVEL in the VGA4 register). The signal is then decimated and filtered in the data filter. Data decision and bit synchronization are as for FSK reception. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 54 MANCHESTER MODE –116 — 19.2 –113 –107 38.4 –103 –104 19.2 51.2 –102 –101 38.4 102.4 –95 –97 76.8 153.6 –92 –94 153.6 307.2 –81 –87 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...

  • Page 55: Crystal Oscillator

    The software will report any contradictions and a more accurate crystal will be recommended if required. XOSC_Q2 XOSC_Q1 XTAL Figure 5-30. Crystal Oscillator Circuit Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...

  • Page 56: Built-In Test Pattern Generator

    Figure 5-31. PN9 Pseudo-random Sequence Generator in TX and RX Mode 5.18 Interrupt on Pin DCLK 5.18.1 Interrupt Upon PLL Lock In synchronous mode the DCLK pin on CC1020 can be used to give an interrupt signal to wake the microcontroller when the PLL is locked. Detailed Description Copyright ©...

  • Page 57: Pa_En And Lna_En Digital Output Pins

    5.18.2 Interrupt Upon Received Signal Carrier Sense In synchronous mode the DCLK pin on CC1020 can also be used to give an interrupt signal to the microcontroller when the RSSI level exceeds a certain threshold (carrier sense threshold). This function can be used to wake or interrupt the microcontroller when a strong signal is received.

  • Page 58: System Considerations And Guidelines

    European countries. In the United States, such devices operate in the 260 to 470 and 902 to 928 MHz bands. CC1020 is also applicable for use in the 950 to 960 MHz frequency band in Japan. A summary of the most important aspects of these regulations can be found in AN001 SRD Regulations For License Free Transceiver Operation (SWRA090).
  • Page 59 SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015 A unique feature in CC1020 is the very fine frequency resolution. This can be used for temperature compensation of the crystal if the temperature drift curve is known and a temperature sensor is included in the system.
  • Page 60 5.20.6 Frequency Hopping Spread Spectrum Systems (FHSS) Due to the very fast locking properties of the PLL, the CC1020 is also very suitable for frequency hopping systems. Hop rates of 1to100 hops/s are commonly used depending on the bit rate and the amount of data to be sent during each transmission.

  • Page 61: Antenna Considerations

    SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015 5.21 Antenna Considerations CC1020 can be used together with various types of antennas. The most common antennas for short- range communication are monopole, helical and loop antennas. Monopole antennas are resonant antennas with a length corresponding to one quarter of the electrical wavelength ( ).

  • Page 62: Configuration Registers

    5.22 Configuration Registers The configuration of CC1020 is done by programming the 8-bit configuration registers. The configuration data based on selected system parameters are most easily found by using the SmartRF Studio software. Complete descriptions of the registers are given in Section 5.22.1.
  • Page 63 CC1020 www.ti.com SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015 Table 5-16. CC1020 Register Overview (continued) ADDRESS ACRONYM REGISTER NAME TEST5 Test register for ADC testing TEST6 Test register for VGA testing TEST7 Test register for VGA testing Status information register (PLL lock, RSSI, calibration ready, and...
  • Page 64 1: LNA_EN pin is “1” when activating external LNA (1) If TF_ENABLE=1 or TA_ENABLE=1 in TEST4 register, then INTERFACE[3:0] controls analog test module: INTERFACE[3] = TEST_PD, INTERFACE[2:0] = TEST_MODE[2:0]. Otherwise, TEST_PD=1 and TEST_MODE[2:0]=001. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 65 Reset calibration logic and lock detector (1) For reset of CC1020 write RESET_N=0 in the MAIN register. The reset register should not be used during normal operation. (2) Bits in the RESET register are self-clearing (will be set to 1 when the reset operation starts). Relevant digital clocks must be running for the resetting to complete.
  • Page 66 8 MSB of frequency control word B Table 5-27. FREQ_1B Register (09h) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE FREQ_1B[7:0] FREQ_B[14:7] — 8 MSB of frequency control word B Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 67 Recommended setting: VCO_CURRENT_A=4 VCO[3:0] VCO_CURRENT_B[3:0] — Control of current in VCO core for frequency B The current steps are the same as for VCO_CURRENT_A Recommended setting: VCO_CURRENT_B=4 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 68 TXDEV_M = deviation × 2 in 804 to 960 MHz band, Decrease TXDEV_X and try again if TXDEV_M < 8. Increase TXDEV_X and try again if TXDEV_M ≥ 16. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 69 30: Decimation clock divisor = 31, 9.91 kHz channel filter BW. 31: Decimation clock divisor = 32, 9.6 kHz channel filter BW. Channel filter bandwidth is 307.2 kHz divided by the decimation clock divisor. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 70 1: Freeze levels for approx. 32 ADC_CLK periods (26 µs) 2: Freeze levels for approx. 64 ADC_CLK periods (52 µs) 3: Freeze levels for approx. 128 ADC_CLK periods (104 µs) Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 71 For automatic power-up sequencing, the AGC_AVG and CS_SET values must be chosen so that carrier sense is available in time to be detected before the chip re-enters power down. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 72 Reference level for Received Signal Strength Indication (carrier sense level) and AGC. Figure 5-15 for an explanation of the relationship between RSSI, AGC and carrier sense settings. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 73 3: Declare lock at counter value 1023, out of lock at value 1007 (1) Set LOCK_SELECT=2 to use the LOCK pin as a lock indicator. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 74 LNAMIX_BIAS — Controls how front-end bias currents are generated 0: Constant current biasing 1: Constant Gm × R biasing (reduces gain variation) Recommended setting: LNAMIX_BIAS=0. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 75 0: Smallest load resistance (smallest swing) … 7: Largest load resistance (largest swing) Recommended settings: TX_SWING=4 for 402 to 470 MHz, TX_SWING=0 for 804 to 960 MHz. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 76 3 (11): Calibration time is approx. 200000 F_REF periods Recommended setting: CAL_WAIT=3 for best accuracy in calibrated PLL loop filter bandwidth. CALIBRATE[3] — — Reserved, write 0 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 77 –1: approx. –0.02° adjustment between I and Q phase 0: approx. +0.02° adjustment between I and Q phase 127: approx. +6.2° adjustment between I and Q phase Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 78 0: Use calibrated value 1: Use VCO_CO[5:0] value VCO_CAL_OVERRIDE controls VCO_CAL_CLK if VCO_CAL_MANUAL=1. Negative transitions are then used to sample VCO_CAL_COMP. TEST3[5:0] VCO_CO[5:0] — VCO_CAL_CURRENT override value Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 79 Override value to second AC coupler in VGA 0: Approx. 0 dB gain 1: Approx. –3 dB gain 2: Approx. –12 dB gain 3: Approx. –15 dB gain Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 80 The relative power is given by RSSI × 1.5 dB in a logarithmic scale. The VGA gain set by VGA_SETTING must be taken into account. See Section 5.9.5 for more details. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 81 — Readout of mixer input to ADC STATUS4[5:3] ADC_I[2:0] — — Readout of ADC “I” output STATUS4[2:0] ADC_Q[2:0] — — Readout of ADC “Q” output Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...
  • Page 82 — — — Not in use, will read 0 STATUS7[4:0] VGA_GAIN_OFFSET[4:0] — — Readout of offset between VGA_SETTING and actual VGA gain set by AGC Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...

  • Page 83: Applications, Implementation, And Layout

    Customers should validate and test their design implementation to confirm system functionality. Application Information Very few external components are required for the operation of CC1020. The recommended application circuit is shown in Figure 6-1. The external components are described in...
  • Page 84 Precision resistor for current reference generator PLL loop filter resistor PLL loop filter resistor PA output match, see Section 5.11 XTAL Crystal, see Section 5.16 Applications, Implementation, and Layout Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020...

  • Page 85: Design Requirements

    50 Ω. Internal circuitry makes it possible to connect the input and output together and match the CC1020 to 50 Ω in both RX and TX mode. However, it is recommended to use an external T/R switch for optimum performance. See Section 5.11...

  • Page 86: Pcb Layout Recommendations

    Do not place a via underneath CC1020 at “pin #1 corner” as this pin is internally connected to the exposed die attached pad, which is the main ground connection for the chip.

  • Page 87: Device And Documentation Support

    To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. Each device has one of three prefixes: X, P, or null (no prefix) (for example, CC1020 is in production; therefore, no prefix is assigned).

  • Page 88: Glossary

    SmartRF, E2E are trademarks of Texas Instruments. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 89 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) CC1020-RTB1 OBSOLETE VQFNP Call TI Call TI -40 to 85 CC1020 CC1020-RTR1 NRND VQFNP Green (RoHS CU NIPDAU...
  • Page 90 PACKAGE OPTION ADDENDUM www.ti.com 7-Mar-2016 Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Lead/Ball Finish - Orderable Devices may have multiple material finish options.
  • Page 91 PACKAGE MATERIALS INFORMATION www.ti.com 21-Nov-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) CC1020RSSR 2500 330.0 16.4 12.0 16.0 CC1020RSST 180.0 16.4 12.0...
  • Page 92 PACKAGE MATERIALS INFORMATION www.ti.com 21-Nov-2016 *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) CC1020RSSR 2500 336.6 336.6 28.6 CC1020RSST 213.0 191.0 55.0 CC1020RUZR VQFNP 336.6 336.6 28.6 Pack Materials-Page 2...
  • Page 95 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.

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