Related Manuals for Texas Instruments DP83640
Summary of Contents for Texas Instruments DP83640
- Page 1 Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 HSMC Ethernet 2-Port 1588 Precision Timing Daughter Board Reference Guide...
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Page 2: Table Of Contents
Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 Table of Contents INTRODUCTION ........................4 FEATURES ..........................5 BOARD DESCRIPTION ......................6 ........................6 LOCK IAGRAM ......................7 OARD OMPONENTS 3.2.1 LEDs .......................... 8 3.2.2 PHY Generic I/O (GPIO), J2, J3 ................8 3.2.3... - Page 3 Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 List of Tables Table 1: RJ45 LEDs ............................ 8 Table 2: PHY 1 Power-Up Strap Options ....................11 Table 3: PHY 2 Power-Up Strap Options ....................12 Table 4: PHY MDIO Addresses ........................13 Table 5: HSMC Connector Pin out ......................14...
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Page 4: Introduction
Reference Guide V1.0 - October 2013 1 Introduction The Nine Ways PhyworkX DP83640 Ethernet Development Kit provides an Ethernet PHY Daughter Board implementing two 10/100 Ethernet copper ports with high precision IEEE 1588 time synchronization support. The board implements two independent Ethernet interfaces with several system interface options and can be used in single and multi-channel applications. -
Page 5: Features
Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 2 Features Two High Performance National DP83640 10/100 Ethernet PHY Integrated IEEE 1588 support with synchronizable timer Auto negotiation for automatic speed selection Automatic cable crossover configuration Reduced Media Independent Interface (RMII) PHY Management Interface (MDIO/MDC) for configuration/status ... -
Page 6: Board Description
Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 3 Board Description 3.1 Block Diagram The Board implements the copper line interfaces using a 2x RJ45 array with integrated magnetics. The MAC interfaces are available at the HSMC connector using 2.5V/3.3V LVTTL/LVCMOS signaling. -
Page 7: Board Components
Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 3.2 Board Components Port0 Port1 genio Figure 3: Board Components... -
Page 8: Leds
Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 3.2.1 LEDs The RJ45 connector provides a green and orange LED on its front side individual per port. Table 1: RJ45 LEDs Description green (l) LED_LINK from PHY: Lit when link up... -
Page 9: Application (Hsmc) General Purpose I/O, J4
Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 The Connector J2 is for Port 0; Connector J3 is for Port 1. Note: gpio9 is connected in-between both PHY devices exclusively to allow synchronization of the internal 1588 timers during operation. -
Page 10: Clock Distribution - Mac Interface Clocking
Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 4 Clock Distribution - MAC Interface Clocking After power-up the PHYs are configured to implement parallel RMII MAC interfaces. PHY1 is configured in RMII master mode and is responsible to generate all necessary clocks for the 2nd PHY (PHY2) as well as the MAC interfaces. -
Page 11: Power-Up Strap Options
Automatic cable crossover is enabled for all ports The optional clk_out clock output of the PHY is enabled Refer to the DP83640 datasheet for full detail. The "wiring" column indicates what kind of strap-option is used on the pin: ... -
Page 12: Phy 2 Strap Options
Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 5.2 PHY 2 Strap Options PHY Address set to 3 Mode set to RMII Slave Auto negotiation is enabled for all ports Automatic cable crossover is enabled for all ports ... -
Page 13: Mdio Management
Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 6 MDIO Management The PHYs can be configured for several modes of operation through the 2-wire MDIO/MDC management interface. Both PHY devices share the same mdio/mdc bus. The PHYs support an MDC clock of up to 25MHz. -
Page 14: High Speed Mezzanine Card (Hsmc) Connector
Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 7 High Speed Mezzanine Card (HSMC) Connector The connector used in HSMC applications is a custom version of the 0.5mm-pitch QTH-DP and mating QSH-DP series from Samtec, Inc. There are three “banks” in this connector. Bank 1 will have every third pin removed as is done in the QSH-DP/QTH-DP series. - Page 15 Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 MDIO ref_clk_x1 rxclk_0 intn_0 txen_0 clk_out_0 3,3 V 12 V txd[1]_0 rxcol_0 txd[0]_0 rxcrs_0 3,3 V 12 V rxerr_0 rxdv_0 3,3 V 12 V rxd[1]_0 rxd[0]_0 3,3 V...
- Page 16 Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 3,3 V 12 V 3,3 V 12 V genio[0] 3,3 V 12 V genio[3] genio[1] genio[4] genio[2] 3,3 V 12 V otp[2] otp[0] otp[3] otp[1] 3,3 V...
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Page 17: Pin Out Description
Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 7.2 Pin out description The following table describes the pin functions. The suffix _0/_1 corresponds to the PHY1/2 respectively. Table 6: HSMC Connector Pin out Description Function/Name... - Page 18 Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 rxcrs_0 (crs_dv) Receive carrier sense/data valid indication from PHY 2. rxd[1:0]_0 RMII receive data rxdv_0 receive data valid from PHY 2 rxer_0 receive error indication from PHY 2...
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Page 19: Plcc-44 Socket
Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 8 PLCC-44 Socket The PLCC-44 Socket allows mounting of an optional OTP device for special purposes. The device has several I/O pins wired to the HMSC connector and operates with 3.3V power supplies. -
Page 20: Table 7: Plcc-44 Socket Pin Description
Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 Table 7: PLCC-44 Socket Pin Description Pin# Function Note Pin# Function Note 3.3V supply 3.3V supply to HSMC, otp[3] to HSMC, otp[2] to HSMC, otp[1] to HSMC, otp[0] to HSMC, otpclk 3.3V supply... -
Page 21: Pin Out For Altera Stratix Ii Gx Pcie Board
Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 9 Pin out for Altera Stratix II GX PCIe Board The following table shows the pin out for the HSMC-A and HSMC-B connectors available on the Stratix-II GX PCIe development board. - Page 22 Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 3,3 V 12 V AD26 led_link_0 gpio4_0 AK38 AD25 led_link_1 gpio4_1 AK37 3,3 V 12 V AE27 gpio8_0 AN39 AE26 gpio8_1 intn_1 AM39 3,3 V 12 V...
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Page 23: Pin Out For Altera Cyclone-Iii Starter Kit Board
Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 10 Pin out for Altera Cyclone-III Starter Kit Board The following table shows the pin out for the HSMC connectors available on the Cyclone-III Starter Kit development board. - Page 24 Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 txd[1]_1 rxerr_1 txd[0]_1 rxdv_1 3,3 V 12 V rxd[1]_1 reset_n rxd[0]_1 3,3 V 12 V led_link_0 gpio4_0 led_link_1 gpio4_1 3,3 V 12 V gpio8_0 gpio8_1 intn_1 3,3 V...
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Page 25: References
Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 11 References DP83640 Precision PHYTER - IEEE 1588 Precision Time Protocol Transceiver, National Semiconductor... -
Page 26: Contact
Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1.0 - October 2013 12 Contact MorethanIP GmbH E-Mail : info@morethanip.com Internet : www.morethanip.com Europe Muenchner Str. 199 D-85757 Karlsfeld Germany : +49 (0) 8131 333939 0 : +49 (0) 8131 333939 1 E-Mail : pbates@nineways.co.uk...