Signal Pin Description; Global Signals - Texas Instruments TLK3134 Data Manual

TLK3134
SLLS838F – MAY 2007 – REVISED DECEMBER 2009
3.5

Signal Pin Description

SIGNAL LOCATION
RST_N P1
ENABLE U1
R16
SPEED[1:0]
N14
PLOOP N16
SLOOP R17
PRBS_EN U2
104 Device Reset Requirements/Procedure
Table 3-1. Global Signals
VOLTAGE TYPE
2.5 V LVCMOS
VDDO
Input
2.5 V LVCMOS
VDDO
Input
2.5 V LVCMOS
VDDO
Input
2.5 V LVCMOS
VDDO
Input
2.5 V LVCMOS
VDDO
Input
2.5 V LVCMOS
VDDO
Input
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DESCRIPTION
Chip Reset (Active Low) When asserted (low logic level), this signal
reinitializes the entire device. Must be held asserted (low logic level) for at
least 10 μS after device power up.
Device Enable.
When this pin is held low, the device is in a low power state.
When high the device operates normally.
A hard or soft reset must be applied after a change of state occurs on this
input signal.
Speed Selection pins. These pins put all four channels of TLK3134 into
one of the three supported (full/half/quarter) channel operation speeds.
00 – All Four Channels in Full Rate mode
01 – All Four Channels in Half Rate mode
10 – All Four Channels in Quarter rate mode
11 – Software Selectable Rate
In the software selectable rate mode, the rate for each channel may be
configured independently by the MDIO interface.
The SPEED[1:0] inputs control both RX and TX directions for all four
channels (Including XAUI and 10GFC modes).
See Appendix A for further
(full/half/quarter) for proper settings as a function of the application mode
and reference clock frequency.
Note that if these pins are not configured on the application board to select
"Software Selectable Rate", then the internal speed register bits cannot be
used to control the rate settings, and the full/half/quarter rate selection is
fixed.
Parallel Loop Enable. When high, the serial output for each channel is
internally looped back to its serial input so that the transmit parallel
interface input data is output onto the receive parallel interface.
Serial Loop Enable. When high, the serial input from each channel is
internally looped back to that channel's serial output, making that channel
a serial repeater. In device configurations where clock tolerance
compensation is not performed in the transmit direction, there are two
options for error free serial loopback operation:
1. Frequency lock (0 ppm) the incoming serial data rate to the local
reference clock device input.
2. Provision the TX SERDES REFCLK to run from a jitter cleaned
version of the RX SERDES RXBCLK (Receive Byte Clock).
PRBS Enable. When this pin is asserted high, the internal PRBS
generator and comparator circuits are enabled on the transmit and receive
data paths of all channels. The PRBS results for each channel can be
read through MDIO counters. Primary chip output signals
GPO3/GPO2/GPO1/GPO0 remain low during PRBS testing when the
input serial stream PRBS pattern is correct, and pulse high when PRBS
errors are detected on the input serial stream on a per channel basis.
GPO3 contains the Channel 3 PRBS currently passing (when low)
indication.
GPO2 contains the Channel 2 PRBS currently passing (when low)
indication.
GPO1 contains the Channel 1 PRBS currently passing (when low)
indication.
GPO0 contains the Channel 0 PRBS currently passing (when low)
indication.
An external loopback connection (via external cables) is required during
PRBS testing.
ST=0:
23
PRBS 2 -1 is transmitted on each transmit channel serial output, and
compared on each receive channel serial input.
ST=1:
7
PRBS 2 -1 is transmitted on each transmit serial output, and compared on
each receive serial input.
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TLK3134
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information on speed selection