Tbid Mode (Ten Bit Interface Ddr); Tbid - Individual Channel Byte Ordering - Channel 0 Example; Tbid - Lane To Functional Pin Mapping - Texas Instruments TLK3134 Data Manual

TLK3134
SLLS838F – MAY 2007 – REVISED DECEMBER 2009

2.7.10 TBID Mode (Ten Bit Interface DDR)

DATA CHANNEL TRANSMIT DATA 10 BITS
NUMBER
Channel 0 {TXC_[4], TXC_[0],TXD_[7:0]}
Channel 1 {TXC_[5],TXC_[1],TXD_[15:8]}
{TXC_[6],TXC_[2],TXD_[23:16] {RXC_[6],RXC_[2],RXD_[23:1
Channel 2
{TXC_[7],TXC_[3],TXD_[31:24] {RXC_[7],RXC_[3],RXD_[31:2
Channel 3
Figure 2-16. TBID – Individual Channel Byte Ordering – Channel 0 Example
30 Detailed Description
Table 2-13. TBID – Lane To Functional Pin Mapping
RECEIVE DATA 10 BITS
(INPUT)
{RXC_[4], RXC_[0],RXD_[7:0]}
RXC_[1],RXD_[15:8]}
}
}
DDR Source Centered Timing
TXCLK_[0]
TXC_[4], TXC_[0],
Data0[9:0]
TXD_[7:0]
RXCLK_[0]
RXC_[4], RXC_[0],
Data0[9:0]
RXD_[7:0]
DDR Source Aligned Timing
TXCLK_[0]
TXC_[4], TXC_[0],
Data0[9:0]
TXD_[7:0]
RXCLK_[0]
RXC_[4], RXC_[0],
Data0[9:0]
RXD_[7:0]
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Product Folder Link(s):
TRANSMIT CLOCK
(OUTPUT)
TXCLK_[0]
{RXC_[5],
TXCLK_[1]
TXCLK_[2]
6]}
TXCLK_[3]
4]}
Data1[9:0]
Data1[9:0]
Data1[9:0]
Data1[9:0]
Copyright © 2007–2009, Texas Instruments Incorporated
TLK3134
RECEIVE CLOCK
(INPUT) (OUTPUT)
RXCLK_ [0]
RXCLK_ [1]
RXCLK_ [2]
RXCLK_ [3]
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