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TLK3134
SLLS838F – MAY 2007 – REVISED DECEMBER 2009
ADDRESS: 0x9601
BIT(s)
NAME
4/5.38401.15
TESTCLKT
ADDRESS: 0x9700
BIT(s)
NAME
MDIO Disable Comp Test
4/5.38656.15
Control
ADDRESS: 0x9800
BIT(s)
NAME
4/5.38912:8
DEBUG_SEL_EN
4/5.38912.7
DIG_TST_OUT_EN
4/5.38912.4:0
DEBUG_SEL
ADDRESS: 0x9900
BIT(s)
NAME
Duty Cycle Correction
4/5.39168.15
Bypass
90
Detailed Description
Table 2-168. TESTCLK_CONTROL
Bit to generate TESTCLKT clock in functional mode.
For TI test purposes only
Table 2-169. BIDI_CMOS_CONTROL
0 = MDIO/MDC Bidi cells automatically detects operating voltage (Default)
1 = MDIO/MDC Bidi cells expects 2.5 V operating voltage
Table 2-170. DEBUG_CONTROL
1 = Sends debug status signals onto debug outputs (GPO)
0 = Debug outputs are tied to 0.
For TI test purposes only
1 = Enables sending DIG TST debug signal onto GPO4
0 = Disables sending DIG TST debug signal onto GPO4.
For TI test purposes only
Debug select bits. For TI test purposes only
Table 2-171. DUTY_CYCLE_CONTROL
1 = Bypasses duty cycle corrected RX/TXBCLK. (Duty cycle set to 40-60,
same clocks as SERDES parallel launch and capture clocks)
0 = Uses duty cycle corrected RX/TXBCLK. (Duty cycle set to 50-50, no
phase relationship to SERDES parallel launch and capture clock)(Default)
For TI test purposes only
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DESCRIPTION
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DESCRIPTION
DEFAULT: 0x0000
DESCRIPTION
Copyright © 2007–2009, Texas Instruments Incorporated
TLK3134
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