4.14 Hstl (Ddr Timing Mode Only) Input Timing Requirements; Hstl (Ddr Timing Mode Only) Source Centered Data Input Timing Requirements; Hstl (Ddr Timing Mode Only) Source Aligned Data Input Timing Requirements - Texas Instruments TLK3134 Data Manual

TLK3134
SLLS838F – MAY 2007 – REVISED DECEMBER 2009

4.14 HSTL (DDR Timing Mode Only) Input Timing Requirements

over operating free-air temperature range (unless otherwise noted)
PARAMETER
t TXDATA setup prior to
setup
TXCLK transition high
or low
t TXDATA hold after
hold
TXCLK transition high
or low
t TXCLK Duty Cycle
duty
t TXCLK Duty Cycle
duty
t TXCLK Period
period
Tfreq TXCLK Frequency
T TXCLK rising or falling
skew
to TXDATA valid.
(1) All typical values are at 25°C and with a nominal supply.
(2) In TBID/NBID Modes Only, the maximum allowed TXCLK period is 33.33 ns.
(3) In TBID/NBID Modes Only, the minimum allowed TXCLK frequency is 30 Mhz.
(4) In TBID/NBID Modes, when the TXCLK is in the 30 → 60 Mhz range, this parameter becomes -0.10 × t
(5) In TBID/NBID Modes, when the TXCLK is in the 30→ 60 Mhz range, this parameter becomes +0.10 × t
TXCLK
V
VDDQ/2
TXDATA
V
Figure 4-9. HSTL (DDR Timing Mode Only) Source Centered Data Input Timing Requirements
TXCLK
V
OH(ac)
TXDATA VDDQ/2
V
OL(ac)
Figure 4-10. HSTL (DDR Timing Mode Only) Source Aligned Data Input Timing Requirements
122 Electrical Specifications
TEST CONDITIONS
Source Centered. See Figure
Note: Input timing reference of VDDQ/2, with ±1 ns/V
rise time on all inputs signals.
Source Centered. See Figure
Note: Input timing reference of VDDQ/2, with ±1 ns/V
rise time on all inputs signals.
Source Centered
Note: Input timing reference of VDDQ/2, with ±1 ns/V
rise time on all inputs signals.
Source Aligned.
Note: Input timing reference of VDDQ/2, with ±1 ns/V
rise time on all inputs signals.
Source Centered and Aligned.
Source Centered and Aligned.
Source Aligned. See Figure
Note: Input timing reference of VDDQ/2, with ±1 ns/V
rise time on all inputs signals.
t
PERIOD
IH(ac)
IL(ac)
Tskew
Submit Documentation Feedback
Product Folder Link(s):
4-9. 0.075 × t
4-9. 0.075 × t
4-10. –0.175 × t
t t
SETUP HOLD
Tskew
Copyright © 2007–2009, Texas Instruments Incorporated
TLK3134
(1)
MIN NOM
period
period
40%
45%
6.25 16.67
(3)
60
+0.175 ×
period
(4)
t
period
period
period
V
IH(ac)
VDDQ/2
V
IL(ac)
t t
SETUP HOLD
V
OH(ac)
VDDQ/2
V
OL(ac)
www.ti.com
MAX UNIT
ps
ps
60%
55%
(2)
ns
160 MHz
ps
(5)