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TLK3134
SLLS838F – MAY 2007 – REVISED DECEMBER 2009
2.7.8 NBI Mode (Nine Bit Interface Mode)
DATA CHANNEL
TRANSMIT DATA 9 BITS
NUMBER
Channel 0
Channel 1
Channel 2
{TXC_[2],TXD_[23:16]}
Channel 3
{TXC_[3],TXD_[31:24]}
TXC_[0],TXD_[7:0]
RXC_[0],RXD_[7:0]
TXC_[0],TXD_[7:0]
RXC_[0],RXD_[7:0]
Figure 2-14. NBI – Individual Channel Byte Ordering – Channel 0 Example
28
Detailed Description
Table 2-11. NBI – Lane To Functional Pin Mapping
RECEIVE DATA 9 BITS
(INPUT)
{TXC_[0],TXD_[7:0]}
{RXC_[0],RXD_[7:0]}
{TXC_[1],TXD_[15:8]}
{RXC_[1],RXD_[15:8]}
{RXC_[2],RXD_[23:16]}
{RXC_[3],RXD_[31:24]}
TXCLK_[0]
Data0[8:0] = {Control Bit, Data Byte}
RXCLK_[0]
Data0[8:0] = {Control Bit, Data Byte}
TXCLK_[0]
Data0[8:0] = {Control Bit, Data Byte}
RXCLK_[0]
Data0[8:0] = {Control Bit, Data Byte}
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TRANSMIT CLOCK
(OUTPUT)
SDR Rising Edge Aligned Timing
Data1[8:0] = {Control Bit, Data Byte}
Data1[8:0] = {Control Bit, Data Byte}
SDR Falling Edge Aligned Timing
Data1[8:0] = {Control Bit, Data Byte}
Data1[8:0] = {Control Bit, Data Byte}
Copyright © 2007–2009, Texas Instruments Incorporated
TLK3134
RECEIVE CLOCK
(INPUT)
(OUTPUT)
TXCLK_[0]
RXCLK_[0]
TXCLK_[1]
RXCLK_[1]
TXCLK_[2]
RXCLK_[2]
TXCLK_[3]
RXCLK_[3]
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