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The level of de-emphasis is programmable via MDIO Register bits. Users can control the strength of the
de-emphasis to optimize for a specific system requirement.
2.7.30 High Speed Receiver
The high speed receiver conforms to the physical layer requirements of IEEE 802.3ae Clause 47(XAUI),
Gigabit Ethernet, and FibreChannel 1 and 2. Register control gives selection between AC and DC
coupling at the receiver. When the receiver is AC coupled, the termination impedances of the receivers
are configured as 100 Ohms with the center tap weakly tied to 0.8 × VDDT with a capacitor to create an
AC ground. When the receiver is DC coupled, the common mode will be determined by both receiver and
transmitter characteristics.
All receive channels incorporate an adaptive equalizer. This circuit compensates for channel insertion loss
by amplifying the high frequency components of the signal, reducing inter-symbol interference.
Equalization can be enabled or disabled per register settings. Both the gain and bandwidth of the
equalizer are controlled by the receiver equalization logic. There are ten available equalization settings.
2.7.31 Loopback
In XAUI Mode, two internal loopback modes are possible for the XAUI Channel Group. One, called XGMII
loopback, allows the data input on the XGMII interface to be returned out the XGMII interface. The other,
called XAUI loopback, allows serial data on the XAUI interface to be returned out the XAUI interface.
In independent channel mode, channels can independently be configured for parallel or serial side
loopback similar to above.
An external loopback (requiring external connection) is also supported, which can be used with the PRBS
patterns, as well as the CJPAT, CRPAT, Mixed/High/Low Frequency tests.
2.7.32 Link Test Functions
The TLK3134 has an extensive suite of built in test functions to support system diagnostic requirements.
Each channel has built-in link test generator and verification logic. Several patterns can be selected via
the MDIO that offer extensive test coverage. The patterns are: 2
Stream), CJPAT, CRPAT, high and low and mixed frequency patterns.
2.7.33 MDIO Management Interface
The TLK3134 supports the Management Data Input/Output (MDIO) Interface as defined in Clauses 22 and
45 of the IEEE 802.3ae Ethernet specification. The MDIO allows register-based management and control
of the serial links. Normal operation of the TLK3134 is possible without use of this interface. However,
some additional features are accessible only through the MDIO.
The MDIO Management Interface consists of a bi-directional data path (MDIO) and a clock reference
(MDC). The device id and port address are determined by control pins (see
device responds as a Clause 22 or Clause 45 device is also determined by control pin ST (see
In Clause 45 (ST = 0), the top 4 control pins PRTAD[4:1] determine the device port address. Note that
TLK3134 can accessed only through even port addresses in Clause 45 mode. In this mode, TLK3134 will
respond if the PHY address field on the MDIO protocol (PA[4:0]) matches {PRTAD[4:1], 1'b0}. PRTAD[0]
pin acts as device id pin where it determines whether TLK3134 is a DTE or PHY device. The device ID is
required to be either 4 (PHY) or 5 (DTE), so only one bit is required to differentiate. If PRTAD[0] is a 0,
then a PHY device is selected for the XGXS. If PRTAD[0] is a 1, then a DTE device is selected for the
XGXS. In this mode, TLK3134 will respond as PHY if the Device address field (DA[4:0]) on the MDIO
protocol is 5'b00100 and as DTE if it is 5'b00101. Note, each register is accessed as either DTE or PHY
devices in the TLK3134, although physically there is only one register accessed two different ways.
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TLK3134
SLLS838F – MAY 2007 – REVISED DECEMBER 2009
7
23
-1 or 2
-1 PRBS (Pseudo Random Bit
Table
3-3). Also, whether the
Detailed Description
TLK3134
Table
3-3).
47
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