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2.7
Parallel Interface Modes - Detailed Description
The TLK3134 has several parallel interface modes. The major parallel interface modes of operation are
presented below:
2.7.1 XAUI/10GFC Mode
Table 2-3. XAUI – Lane To Functional Pin Mapping (XAUI_ORDER = 1)
TRANSMIT
XAUI LANE
CONTROL BIT
(INPUT)
Lane 3
TXC_[3]
Lane 2
TXC_[2]
Lane 1
TXC_[1]
Lane 0
TXC_[0]
Table 2-4. 10GFC – Lane To Functional Pin Mapping (XAUI_ORDER = 0)
TRANSMIT
10GFC LANE
CONTROL BIT
(INPUT)
Lane 0
TXC_[3]
Lane 1
TXC_[2]
Lane 2
TXC_[1]
Lane 3
TXC_[0]
Copyright © 2007–2009, Texas Instruments Incorporated
TRANSMIT
RECEIVE
DATA BYTE
CONTROL BIT
(INPUT)
(OUTPUT)
TXD_[31:24]
RXC_[3]
TXD_[23:16]
RXC_[2]
TXD_[15:8]
RXC_[1]
TXD_[7:0]
RXC_[0]
TRANSMIT
RECEIVE
DATA BYTE
CONTROL BIT
(INPUT)
(OUTPUT)
TXD_[31:24]
RXC_[3]
TXD_[23:16]
RXC_[2]
TXD_[15:8]
RXC_[1]
TXD_[7:0]
RXC_[0]
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Product Folder Link(s):
SLLS838F – MAY 2007 – REVISED DECEMBER 2009
RECEIVE
TRANSMIT
CONTROL BYTE
CLOCK
(OUTPUT)
(INPUT)
RXD_[31:24]
TXCLK_[1]
RXD_[23:16]
TXCLK_[1]
RXD_[15:8]
TXCLK_[1]
RXD_[7:0]
TXCLK_[1]
RECEIVE
TRANSMIT
CONTROL BYTE
CLOCK
(OUTPUT)
(INPUT)
RXD_[31:24]
TXCLK_[1]
RXD_[23:16]
TXCLK_[1]
RXD_[15:8]
TXCLK_[1]
RXD_[7:0]
TXCLK_[1]
TLK3134
TLK3134
RECEIVE
CLOCK
(OUTPUT)
RXCLK_[1]
RXCLK_[1]
RXCLK_[1]
RXCLK_[1]
RECEIVE
CLOCK
(OUTPUT)
RXCLK_[1]
RXCLK_[1]
RXCLK_[1]
RXCLK_[1]
Detailed Description
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