Interrupt Status Register; End-Of-Interrupt Register - Intel 80C186XL User Manual

INTERRUPT CONTROL UNIT
Register Name:
Register Mnemonic:
Register Function:
15
N
S
P
E
C
Bit
Mnemonic
NSPEC Nonspecific
EOI
VT4:0 Interrupt
Type
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
8.4.8

Interrupt Status Register

The Interrupt Status register (Figure 8-14) contains the DMA Halt bit and one bit for each timer
interrupt. The CPU sets the DMA Halt bit to suspend DMA transfers while an NMI is processed.
Software can also read and write this bit. See "Suspension of DMA Transfers" on page 10-20 for
details. A timer bit is set to indicate a pending interrupt and is cleared when the interrupt request
is acknowledged. Any number of bits can be set at any one time.
8-22

End-of-Interrupt Register

EOI
Used to issue an EOI command
Reset
Bit Name
State
0
0 0000
Figure 8-13. End-of-Interrupt Register
V
T
4
Function
Set to issue a nonspecific EOI.
Write with the interrupt type of the interrupt
whose In-Service bit is to be cleared.
0
V V V
V
T T T T
3 2 1 0
A1210-A0