Pacs Register Definition - Intel 80C186XL User Manual

CHIP-SELECT UNIT
Register Name:
Register Mnemonic:
Register Function:
15
U U U
1 1 1
9 8 7
Bit
Mnemonic
U19:13 Start
Address
R2 Bus Ready
Disable
R1:0 Wait State
Value
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products. U19:16 must be
programmed to zero for proper I/O bus cycle operation. Reading this register and
the MPCS register (before writing them) enables the PCS chip-selects; however,
none of the programmable fields will be properly initialized.
6-10
PCS Control Register
PACS
Controls the operation of the PCS chip-selects.
U U U U
1 1 1 1
6 5 4 3
Reset
Bit Name
State
XXH
X
3H
Figure 6-8. PACS Register Definition
Function
Defines the starting address for the block of
PCS chip-selects. During memory or I/O bus
cycles, U19:13 are compared with the A19:13
address bits. An equal to or greater than result
enables the PCS chip-select. U19:16 must be
programmed to zero for proper I/O bus cycle
operation.
When R2 is clear, bus ready must be active to
complete a bus cycle. When R2 is set, R1:0
control the number of bus wait states and bus
ready is ignored.
R1:0 define the minimum number of wait states
inserted into the bus cycle.
0
R R R
2 1 0
A1143-0B