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Register Name:
Register Mnemonic:
Register Function:
15
D
D
D
M
D
I
N
E
E
M
C
C
Bit
Bit Name
Mnemonic
CHG
Change
Start Bit
STRT
Start DMA
Channel
WORD
Word
Transfer
Select
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a
logic zero to ensure compatibility with future Intel products.
Figure 10-11. DMA Control Register (Continued)
10.2.1.3
Selecting the Source of DMA Requests
DMA requests can come from either an internal source (Timer 2) or an external source.
Internal DMA requests are selected by setting the IDRQ bit in the DMA Control Register (see
Figure 10-11 on page 10-15) for the channel. The DMA channel ignores its DRQ pin when inter-
nal requests are programmed. Similarly, the DMA channel responds only to the DRQ pin (and
ignores internal requests) when external requests are selected.
DMA Control Register
DxCON
Controls DMA channel parameters.
S
S
S
T
I
M
D
I
C
N
E
N
T
E
M
C
C
Reset
State
X
Set CHG to enable modifying the STRT bit.
0
Set STRT to arm the DMA channel. The STRT bit can
be modified only when the CHG bit is set.
X
Set WORD to select word transfers; clear WORD to
select byte transfers. The 8-bit bus versions of the
device ignore the WORD bit.
DIRECT MEMORY ACCESS UNIT
S
S
P
I
Y
Y
D
N
N
R
1
0
Q
Function
0
C
S
W
H
T
O
G
R
R
T
D
A1180-0A
10-17
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