Intel 80C186XL User Manual page 401

INDEX
F
Fault exceptions, 2-43
FaxBack service, 1-4
F-Bus
and PCB, 4-5
operation, 4-5
Flags‚ See Processor Status Word (PSW)
Floating Point, defined, 2-37
H
HALT bus cycle‚ See Bus cycles
HOLD/HLDA protocol‚ See Bus hold protocol
Hypertext manuals, obtaining from BBS, 1-5
I
I/O devices
interfacing with, 3-6–3-7
memory-mapped, 3-6
I/O ports
addressing, 2-36
I/O space, 3-1–3-7
accessing, 3-6
reserved locations, 2-15, 6-17
Idle states
and bus cycles, 3-18
Immediate operands, 2-28
IMUL instruction, A-9
Inputs, asynchronous, synchronizing, B-1
INS instruction, A-2
In-Service register, 8-5, 8-7, 8-18, 8-19, 8-28
Instruction Pointer (IP), 2-1, 2-6, 2-13, 2-23, 2-39,
2-41
reset status, 2-6
Instruction prefetch bus cycle‚ See Bus cycles
Instruction set, 2-17, A-1, D-1
additions, A-1
arithmetic instructions, 2-19–2-20, A-9
bit manipulation instructions, 2-21–2-22, A-9
data transfer instructions, 2-18–2-20, A-1,
A-8
data types, 2-37–2-38
enhancements, A-8
high-level instructions, A-2
nesting, A-2
processor control instructions, 2-27
program transfer instructions, 2-23–2-24
reentrant procedures, A-2
Index-4
rotate instructions, A-10
shift instructions, A-9
string instructions, 2-22–2-23, A-2
INT instruction, single-byte‚ See Breakpoint
interrupt
INT0 instruction, 2-44
INTA bus cycle‚ See Bus cycles
Integer, defined, 2-37, 10-7
Interrupt Control register, 8-28
Interrupt Control registers, 8-12
for external pins, 8-14, 8-15
for internal sources, 8-13
Interrupt Control Unit (ICU), 8-1–8-31
block diagram, 8-2, 8-24
cascade mode, 8-7
initializing, 8-30, 8-31
interfacing with an 82C59A Programmable
Interrupt Controller, 3-25–3-27
master mode, 8-1, 8-2–8-23
initializing, 8-30
operation in slave mode, 8-29
operation with nesting, 8-4
programming, 8-11, 8-25
registers, 8-11, 8-25
master mode, 8-11
slave mode, 8-1, 8-23–8-30
special fully nested mode, 8-8
with cascade mode, 8-8
without cascade mode, 8-8
typical interrupt sequence, 8-5
Interrupt Enable Flag (IF), 2-7, 2-9, 2-41
Interrupt Mask register, 8-16, 8-17, 8-28
Interrupt Request register, 8-16, 8-28
Interrupt Status register, 8-7, 8-22, 8-23, 8-28
Interrupt Vector register, 8-26, 8-27
Interrupt Vector Table, 2-39, 2-40
Interrupt-on-overflow trap (Type 4 exception),
2-44
Interrupts, 2-39–2-43
and CSU initialization, 6-6
controlling priority, 8-12
edge- and level-sensitive, 8-10
and external 8259As, 8-10
enabling cascade mode, 8-12
enabling special fully nested mode, 8-12
latency, 2-45
reducing, 3-28
latency and response times, 8-10, 8-11, 8-30