Slave Mode; Interrupt Status Register - Intel 80C186XL User Manual

Register Name:
Register Mnemonic:
Register Function:
15
D
H
L
T
Bit
Mnemonic
DHLT DMA Halt
TMR2:0 Timer
Interrupt
Pending
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
Do not write to the DHLT bit while Timer/Counter Unit interrupts are enabled.
A conflict with the internal use of the register may cause incorrect processing
of timer interrupts.
The DHLT bit does not function when the interrupt controller is in slave mode.
8.5

SLAVE MODE

Although Master mode is the most common, Slave mode is useful in larger system designs. In
Slave mode, an external 8259A module controls the interrupt input to the CPU and acts as the
master interrupt controller. The Interrupt Control Unit processes only the internal interrupt re-
quests and acts as an interrupt input to the external 8259A. In simplest terms, the Interrupt Control
Unit behaves like a cascaded 8259A to the master 8259A. (See Figures 8-15 and 8-16.)

Interrupt Status Register

INTSTS
Indicates pending shared-source interrupts and
DMA suspension
Reset
Bit Name
State
0
000
Figure 8-14. Interrupt Status Register
NOTE
INTERRUPT CONTROL UNIT
Function
This bit is set to suspend DMA activity.
A bit is set to indicate a pending interrupt from
the corresponding timer.
0
T T T
M M M
R R R
2 1 0
A1193-A0
8-23