Poll Register - Intel 80C186XL User Manual

INTERRUPT CONTROL UNIT
Reading the Poll register (Figure 8-11) acknowledges the pending interrupt, just as if the CPU
had started the interrupt vectoring sequence. The Interrupt Control Unit updates the Interrupt Re-
quest, In-Service, Poll, and Poll Status registers, as it does in the normal interrupt acknowledge
sequence. However, the processor does not run an interrupt acknowledge sequence or fetch the
vector from the vector table. Instead, software must read the interrupt type and execute the proper
routine to service the pending interrupt.
Reading the Poll Status register (Figure 8-12) will merely transmit the status of the polling bits
without modifying any of the other Interrupt Controller registers.
Register Name:
Register Mnemonic:
Register Function:
15
I
R
E
Q
Bit
Mnemonic
IREQ Interrupt
Request
VT4:0 Vector Type
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
8-20

Poll Register

POLL
Read to check for and acknowledge pending
interrupts when polling
Reset
Bit Name
State
0
0
Figure 8-11. Poll Register
V
T
4
Function
This bit is set to indicate a pending interrupt.
Contains the interrupt type of the highest
priority pending interrupt.
0
V V V V
T T T T
3 2 1 0
A1208-A0