Regaining Bus Control To Run A Dram Refresh Bus Cycle - Intel 80C186XL User Manual

T1
CLKOUT
HOLD
HLDA
AD15:0
DEN
RD, WR,
BHE, S2:0
DT / R,
A19:16
NOTES:
1. HLDA is deasserted; signaling need to run DRAM refresh cycles less than T CLHAV .
2. External bus master terminates use of the bus.
3. HOLD deasserted; greater than T HVCL .
4. Hold may be reasserted after one clock.
5. Lines come out of float in order to run DRAM refresh cycle.
Figure 7-9. Regaining Bus Control to Run a DRAM Refresh Bus Cycle
T1 T1
3
1
2
REFRESH CONTROL UNIT
T1 T1
4
5
T4 T1
6
A1534-0A
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