Enabling/Disabling Counters; Txout Signal Timing - Intel 80C186XL User Manual

TIMER/COUNTER UNIT
Timer 0
Serviced
1
Internal Count Value Maxcount - 1 0
TxOUT Pin
NOTE: 1. T
CLOV1
A1301-0A
Figure 9-9. TxOUT Signal Timing
In dual maximum count mode, the timer output pin indicates which Maxcount Compare register
is currently in use. A low output indicates Maxcount Compare B, and a high output indicates
Maxcount Compare A (see Figure 9-4 on page 9-6). If programmed to run continuously, a repet-
itive waveform can be generated. For example, if Maxcount Compare A contains 10, Maxcount
Compare B contains 20, and CLKOUT is 12.5 MHz, the timer generates a 33 percent duty cycle
waveform at 104 KHz. The output pin always goes high at the end of the counting sequence (even
if the timer is not programmed to run continuously).
9.2.5

Enabling/Disabling Counters

Each timer has an Enable (EN) bit in its Control register to allow or prevent timer counting. The
Inhibit (INH) bit controls write accesses to the EN bit. Timers 0 and 1 can be programmed to use
their input pins as enable functions also. If a timer is disabled, the count register does not incre-
ment when the counter element services the timer.
The Enable bit can be altered by programming or the timers can be programmed to disable them-
selves at the end of a counting sequence with the Continuous (CONT) bit. If the timer is not pro-
grammed for continuous operation, the Enable bit automatically clears at the end of a counting
sequence. In single maximum count mode, this occurs after Maxcount Compare A is reached. In
dual maximum count mode, this occurs after Maxcount Compare B is reached (Timers 0 and 1
only).
9-15