Considerations For The 80C187 Math Coprocessor Interface - Intel 80C186XL User Manual

As an example, to relocate the Peripheral Control Block to the memory range 10000-100FFH, the
user would program the PCB Relocation Register with the value 1100H. Since the Relocation
Register is part of the Peripheral Control Block, it relocates to word 10000H plus its fixed offset.
Due to an internal condition, external ready is ignored if the device is
configured in Cascade mode and the Peripheral Control Block (PCB) is
located at 0000H in I/O space. In this case, wait states cannot be added to
interrupt acknowledge bus cycles. However, you can add wait states to
interrupt acknowledge cycles if the PCB is located at any other address.
4.5.1

Considerations for the 80C187 Math Coprocessor Interface

Systems using the 80C187 math coprocessor interface must not relocate the Peripheral Control
Block to location 0000H in I/O space. The 80C187 interface uses I/O locations 0F8H through
0FFH. If the Peripheral Control Block resides in these locations, the processor communicates
with the Peripheral Control Block, not the 80C187 interface circuitry.
If the PCB is located at 0000H in I/O space and access to the math coprocessor
interface is enabled (the Escape Trap bit is clear), a numerics (ESC) instruction
causes indeterminate system operation.
Since the 8-bit bus version of the device does not support the 80C187, it automatically traps an
ESC instruction to the Type 7 interrupt, regardless of the state of the Escape Trap (ET) bit.
For details on the math coprocessor interface, see Chapter 11, "Math Coprocessing."
PERIPHERAL CONTROL BLOCK
NOTE
NOTE
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