MATH COPROCESSING
External
Oscillator
AD15:0
ALE
CLKOUT
80C186
Modular
Core
RESET
WR
RD
BUSY
ERROR
PEREQ
NCS
CS
DEN
DT/R
Figure 11-3. 80C187 Configuration with a Partially Buffered Bus
11-12
Latch
A15:0
A1
A2
EN
CKM
CLK
80C187
RESET
NPWR
NPRD
BUSY
ERROR
PEREQ
NPS1
NPS2
Buffer
1
T OE
2
Buffer
T OE
D15:8
D7:0
D15:0
A1530-0A