Intel 80C186XL User Manual page 393

Intel microprocessor user's manual
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INSTRUCTION SET OPCODES AND CLOCK CYCLES
Table D-4. Mnemonic Encoding Matrix (Left Half)
x0
ADD
0x
b,f,r/m
ADC
1x
b,f,r/m
AND
2x
b,f,r/m
XOR
3x
b,f,r/m
INC
4x
AX
PUSH
5x
AX
PUSHA
6x
JO
7x
Immed
8x
b,r/m
NOP
(XCHG)
9x
AX
MOV
Ax
m AL
MOV
Bx
i AL
Shift
Cx
b,i
Shift
Dx
b
LOOPNZ/
LOOPNE
Ex
LOCK
Fx
NOTE: Table D-5 defines abbreviations used in this matrix. Shading indicates reserved opcodes.
D-20
x1
x2
x3
ADD
ADD
ADD
w,f,r/m
b,t,r/m
w,t,r/m
ADC
ADC
ADC
w,f,r/m
b,t,r/m
w,t,r/m
AND
AND
AND
w,f,r/m
b,t,r/m
w,t,r/m
XOR
XOR
XOR
w,f,r/m
b,t,r/m
w,t,r/m
INC
INC
INC
CX
DX
BX
PUSH
PUSH
PUSH
CX
DX
BX
POPA
BOUND
w,f,r/m
JNO
JB/
JNB/
JNAE/
JAE/
JC
JNC
Immed
Immed
Immed
w,r/m
b,r/m
is,r/m
XCHG
XCHG
XCHG
CX
DX
BX
MOV
MOV
MOV
m AX
AL m
AX m
MOV
MOV
MOV
i CL
i DL
i BL
Shift
RET
RET
w,i
(i+SP)
Shift
Shift
Shift
w
b,v
w,v
LOOPZ/
LOOP
JCXZ
LOOPE
REP
REP
z
x4
x5
x6
ADD
ADD
PUSH
b,ia
w,ia
ES
ADC
ADC
PUSH
b,i
w,i
SS
AND
AND
SEG
b,i
w,i
=ES
XOR
XOR
SEG
b,i
w,i
=SS
INC
INC
INC
SP
BP
SI
PUSH
PUSH
PUSH
SP
BP
SI
JE/
JNE/
JBE/
JZ
JNZ
JNA
TEST
TEST
XCHG
b,r/m
w,r/m
b,r/m
XCHG
XCHG
XCHG
SP
BP
SI
MOVS
MOVS
CMPS
MOV
MOV
MOV
i AH
i CH
i DH
LES
LDS
MOV
b,i,r/m
AAM
AAD
IN
IN
OUT
HLT
CMC
Grp1
b,r/m
x7
POP
ES
POP
SS
DAA
AAA
INC
DI
PUSH
DI
JNBE/
JA
XCHG
w,r/m
XCHG
DI
CMPS
MOV
i BH
MOV
w,i,r/m
XLAT
OUT
Grp1
w,r/m

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