Table of Contents
Advertisement
Register Name:
Register Mnemonic:
Register Function:
15
Bit
Mnemonic
T4:0
Interrupt
Vector Type
Field
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
Figure 8-17. Interrupt Vector Register (Slave Mode Only)
8.5.1.2
End-Of-Interrupt Register
The End-of-Interrupt (EOI) register has the same function in Slave mode as in Master mode.
However, non-specific EOI commands are not supported, so the NSPEC bit is omitted from the
register. Only specific EOI commands can be issued. To clear an In-Service bit in Slave mode,
write the three least-significant bits of the interrupt type (from Table 8-5) to the VT2:0 bits.
Interrupt Vector Register (Slave Mode only)
INTVEC
Specifies the five most-significant bit of the interrupt
vector types for the internal interrupt sources
Reset
Bit Name
State
00000
INTERRUPT CONTROL UNIT
T
4
Function
Specifies the five most-significant bits of the
interrupt vector types for the internal interrupt
sources. The three least-significant bits are
fixed (see Table 8-5).
0
T
T
T
T
3
2
1
0
A1196-A0
8-27
Advertisement
Table of Contents
