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The Refre
h Control Unit (RCU) simplifies dynamic memory controller design with its integrat-
s
ed address and clock counters. Figure 7-1 shows the relationship between the Bus Interface Unit
and the Refresh Control Unit. Integrating the Refresh Control Unit into the processor allows an
external DRAM controller to use chip-selects, wait state logic and status lines.
CPU
Clock
F-Bus
Refresh Clock
Interval Register
9-Bit Down
Counter
CLR
REQ
Refresh Control
Register
Refresh Base
Address Register
7
Refresh Address
Figure 7-1. Refresh Control Unit Block Diagram
REFRESH CONTROL UNIT
Refresh Request
Refresh Acknowledge
9-Bit Address Counter
Refresh Address
Register
13
20-Bit
CHAPTER 7
BIU
Interface
A1539-01
7-1
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