Interrupt Acknowledge Bus Cycle; Write Cycle Critical Timing Parameters - Intel 80C186XL User Manual

The minimum device data hold time (from WR high) is defined by T
must be greater than the minimum device requirements; however, the value can be changed only
by decreasing the clock rate.
Table 3-5. Write Cycle Critical Timing Parameters
Memory Device
Parameter
T
WC
T
AW
T
CW
T
WR
T
DW
T
DH
T
WP
T and T define the minimum time (maximum frequency) a device can process write bus cy-
WC WP
cles. T determines the minimum time from the end of the current write cycle to the start of the
WR
next write cycle. All three parameters require that calculated values be greater than device re-
quirements. The calculated T
culated T value, however, can be changed only by decreasing the clock rate.
WR
3.5.3

Interrupt Acknowledge Bus Cycle

Interrupt expansion is accomplished by interfacing the Interrupt Control Unit with a peripheral
device such as the 82C59A Programmable Interrupt Controller. (See Chapter 8, "Interrupt Con-
trol Unit," for more information.) The BIU controls the bus cycles required to fetch vector infor-
mation from the peripheral device, then passes the information to the CPU. These bus cycles,
collectively known as Interrupt Acknowledge bus cycles, operate similarly to read bus cycles.
However, instead of generating RD to enable the peripheral, the INTA signal is used. Figure 3-23
illustrates a typical Interrupt Acknowledge (or INTA) bus cycle.
An Interrupt Acknowledge bus cycle consists of two consecutive bus cycles. LOCK is generated
to indicate the sequential bus operation. The second bus cycle strobes vector information only
from the lower half of the bus (D7:0). In a 16-bit bus system, the upper half of the bus (D15:8)
floats.
Description
Write cycle time
Address valid to end of write strobe (WR high)
Chip enable (LCS) to end of write strobe (WR high)
Write recover time
Data valid to write strobe (WR high)
Data hold from write strobe (WR high)
Write pulse width
and T values increase with the insertion of wait states. The cal-
WC WP
BUS INTERFACE UNIT
. The calculated value
DH
Equation
4T
CLCL
3T – T
CLCL ADLTCH
3T
CLCL
T
WHLH
2T
CLCL
T
WHDX
T
WLWH
3-25