Intel 80C186XL User Manual page 398

80C187 Math Coprocessor, 10-2–10-8
accessing, 10-10–10-11
arithmetic instructions, 10-3–10-4
bus cycles, 10-11
clocking, 10-10
code examples, 10-13–10-16
comparison instructions, 10-5
constant instructions, 10-6
data transfer instructions, 10-3
data types, 10-7–10-8
design considerations, 10-10–10-11
example floating point routine, 10-16
exceptions, 10-13
I/O port assignments, 10-10
initialization example, 10-13–10-16
instruction set, 10-2
interface, 10-7–10-13
and chip-selects, 6-17, 10-11
and PCB location, 4-7
exception trapping, 10-13
generating READY, 10-11
processor control instructions, 10-6
testing for presence, 10-10
transcendental instructions, 10-5
8259A Programmable Interrupt Controllers, 8-1
and special fully nested mode, 8-8
cascading, 8-7, 8-8
interrupt type, 8-9
priority structure, 8-8
82C59A Programmable Interrupt Controller
interfacing with, 3-25–3-27
A
Address and data bus, 3-1–3-6
16-bit, 3-1–3-5
considerations, 3-7
8-bit, 3-5–3-6
considerations, 3-7
See also Bus cycles‚ Data transfers
Address bus, See Address and data bus
Address space, See Memory space‚ I/O space
Addressing modes, 2-27–2-36
and string instructions, 2-34
based, 2-30, 2-31, 2-32
based index, 2-34, 2-35
direct, 2-29
immediate operands, 2-28
indexed, 2-32, 2-33
indirect, 2-36
memory operands, 2-28
register indirect, 2-30, 2-31
register operands, 2-27
AH register, 2-5
AL register, 2-5, 2-18, 2-23
ApBUILDER files, obtaining from BBS, 1-5
Application BBS, 1-5
Architecture
CPU block diagram, 2-2
device feature comparisons, 1-2
family introduction, 1-1
overview, 1-1, 2-1
ARDY, See READY
Arithmetic
instructions, 2-19–2-20
interpretation of 8-bit numbers, 2-20
Arithmetic Logic Unit (ALU), 2-1
Array bounds trap (Type 5 exception), 2-44
ASCII, defined, 2-37
Auxiliary Flag (AF), 2-7, 2-9
AX register, 2-1, 2-5, 2-18, 2-23, 3-6
B
Base Pointer (BP)‚ See BP register
BBS, 1-5
BCD, defined, 2-37
Bit manipulation instructions, 2-21–2-22
BOUND instruction, 2-44, A-8
BP register, 2-1, 2-13, 2-30, 2-34
Breakpoint interrupt (Type 3 exception), 2-44
Bulletin board system (BBS), 1-5
Bus cycles, 3-20–3-45
address/status phase, 3-10–3-12
and 80C187, 10-11
and CSU, 6-17
and PCB accesses, 4-4
and T-states, 3-9
data phase, 3-13
HALT cycle, 3-28–3-33
INDEX
Index-1