Chip-Select Unit Functional Overview; Common Chip-Select Generation Methods - Intel 80C186XL User Manual

CHIP-SELECT UNIT
27C256
A0:12
A1:13
RD OE
A16
CS
(A)
Chip-Selects Using
Addresses Directly
Figure 6-1. Common Chip-Select Generation Methods
6.3

CHIP-SELECT UNIT FUNCTIONAL OVERVIEW

The Chip-Select Unit (CSU) decodes bus cycle address and status information and enables the
appropriate chip-select. Figure 6-3 illustrates the timing of a chip-select during a bus cycle. Note
that the chip-select goes active in the same bus state as address goes active, eliminating any delay
through address latches and decoder circuits. The Chip-Select Unit activates a chip-select for bus
cycles initiated by the CPU, DMA Control Unit or Refresh Control Unit.
Six of the chip-selects map only into memory address space, while the remaining seven can map
into either memory or I/O address space. The chip-selects typically associate with memory and
peripheral devices as follows:
6-2
74AC138
A19 A3
D7:0
A18 A2
A17 A1
D15:8
E1
ALE
E2
HLDA
E3
Chip-Selects Using
Simple Decoder
Selects 896K to 1M
Y7
Selects 768K to 896K
Y6
Y5
Y4
Y3
Y2
Selects 128K to 256K
Y1
Selects 0 to 128K
Y0
(B)
A1168-0A