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Figure 44.
4.7
4.7.1
4.7.1.1
4.7.1.1.1
Hardware Design Guide
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Voltage QDR V
Divider Example for Each QDR Channel
REF
VDDQ 1.5 V
549
1%
549
1%
VDDQ 1.5 V
549
1%
549
1%
VDDQ 1.5 V
549
1%
549
1%
TCAM/SRAM/Coprocessor Interface
In certain cases it may be desirable to implement a connector in the QDR interface to accommodate
a third-party QDRII-LA1-compliant coprocessor or an upgradable QDR memory module. The
Intel BKM for this is to provide the IXP28XX QDR interface through a 2 x 57 shrouded 114-pin
Mictor* connector. The connector has all the QDR signals from a single channel and JTAG
interface. In addition, power is provided in the form of 1.5 V, 1.8 V, and 3.3 V. The current for the
1.5 V and 1.8 V is limited to 0.5 A and 2.5 A, respectively. This current supply provides the power
support for up to four QDRII SRAMs.
TCAM/SRAM/Coprocessor Interface — Base Card Side
This part of the interface runs between the ingress IXP28XX network processor and the Mictor*
connector on the base card side. All traces are matched in length to within ±10 mils and have the
same nominal line impedance of 50 Ω.
Interface Topologies
This part of the interface has a topology of a point-to-point configuration between the IXP28XX
network processor's I/O buffer and the Mictor* connector. The rest of the topologies are found on
the TCAM/SRAM/coprocessor card and are different for different signals (Address, D, etc.).
Address, D, CONTROL, Q, and K-Clocks Signals
Figure 45
illustrates topologies for address, D, CONTROL, Q, and K-clocks.
VREF0 0.75 V
VREF1 0.75 V
VREF2 0.75 V
VREF3 0.75 V
VDDQ 1.5 V
549
1%
549
1%
IXP28XX Network Processor
QDR SRAM
®
ntel
XP2800
Network Processor
VREF_QDR0
VREF_QDR1
VREF_QDR2
VREF_QDR3
3778-02
81
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