13. The actual counter that counts the number of idles since the last character was received. For example,
the time that a character takes to arrive (corresponds to idle) at 9600 baud is 1 msec.
14. Break register.
15. The number of times the parity error occurred during the reception of a single byte.
16. The number of times the framing error occurred during the reception of a single byte.
17. The number of times the noise error occurred during the reception of a single byte.
18. The number of times a break signal (end of reception) was received at the port.
19. Not in use.
20. Control character register
21. The characters that are used to close a frame.
## 287
UART hardware data buffers status :-
Internal software data (key)
Internal hardware registers
Internal hardware parameters
Receive buffer descriptor 0
Receive buffer descriptor 1
Receive buffer descriptor 2
Receive buffer descriptor 3
Receive buffer descriptor 4
Receive buffer descriptor 5
Receive buffer descriptor 6
Receive buffer descriptor 7
Transmit buffer descriptor 0
Transmit buffer descriptor 1
Transmit buffer descriptor 2
Transmit buffer descriptor 3
Transmit buffer descriptor 4
Transmit buffer descriptor 5
Transmit buffer descriptor 6
Transmit buffer descriptor 7
Rxd/Txd function code
Maximum receive buffer length
Current receive buffer status
Current receive buffer offset
Current receive data pointer
Current receive byte counter
Current receive temp memory
Current transmit buffer status
Current transmit buffer offset
Current transmit data pointer
Current transmit byte counter
Current transmit temp memory
1. Device key address.
2. H-W registers address.
(DATA)
: %% 1
(IREG)
: %% 2
(IRAM)
: %% 3
(RXBD0) : %%
(RXBD1) : %%
(RXBD2) : %%
(RXBD3) : %%
(RXBD4) : %%
(RXBD5) : %%
(RXBD6) : %%
(RXBD7) : %%
(TXBD0) : %%
(TXBD1) : %%
(TXBD2) : %%
(TXBD3) : %%
(TXBD4) : %%
(TXBD5) : %%
(TXBD6) : %%
(TXBD7) : %%
(R/TFCR): %% 20
(MRBLR) : %% 21
: %% 22
(RBD#) : %% 23
: %%
: %% 24
: %% 24
: %% 25
(TBD#)
: %% 26
: %%
: %% 27
: %% 27
C-34
Software Diagnostics Output
%%
%%
%% 4
%%
%%
%% 5
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%%
%% 6
%%
%%
%% 7
%%
%%
%% 8
%%
%%
%% 9
%%
%%
%% 10
%%
%%
%% 11
%%
%%
%% 12
%%
%%
%% 13
%%
%%
%% 14
%%
%%
%% 15
%%
%%
%% 16
%%
%%
%% 17
%%
%%
%% 18
%%
%%
%% 19
%% 24
%% 27