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3. The storage address in INSERT STORAGE
KEY or SET STORAGE KEY does not have
zeros in the four low-order bit positions.
4. An odd-numbered general register is designated
by an R field of an instruction that requires an
even-numbered register designation.
5. A floating-point register other than 0, 2, 4, or 6
is specified for a short or long operand, or a
floating-point register other than 0 or 4 is
specified for an extended operand.
6. The multiplier or divisor in decimal arithmetic
exceeds 15 digits and sign.
7. The length of the first-operand field is less than
or equal to the length of the second-operand
field in decimal multiplication or division.
8. Bit positions 8-11 of MONITOR CALL do not
contain zeros.
9. A one is introduced into an unassigned bit
position of an EC-mode PSW (bit positions 0,
2-5, 16, 17, and 24-39).
10. Page 0 is designated to become connected or
disconnected.
The execution of the instruction identified by the
old PSW is suppressed. However, for cause 9, the
operation that introduces the new PSW is
completed, but an interruption occurs immediately
thereafter.
When the instruction address is odd (cause 1),
the instruction-length code (ILC) is 1, 2, or 3,
indicating the multiple of 2 by which the
instruction address has been incremented. It is
unpredictable whether the ILC is 1, 2, or'3.
For causes 2-8 and 10, the ILC is 1,2, or 3,
designating the length of the instruction causing the
exception.
When the exception is recognized because of
cause 9, and the invalid bit value has been
introduced by LOAD PSW or an interruption, the
ILC is
o.
When the exception due to cause 9 is
introduced by SET SYSTEM MASK or STORE
THEN OR SYSTEM MASK, the ILC is 2.
See the section "Exceptions Associated with the
PSW" in this chapter for a discussion of when the
exceptions associated with the PSW are recognized.
Recognition of Access Exceptions
The addressing, page-access, and protection
exceptions are collectively referred to as access
exceptions.
Any access exception is recognized as part of the
execution of the instruction with which the
exception is associated. An access exception is not
recognized when the CPU has made an attempt to
fetch from an inaccessible location or has detected
some other access-exception condition, but a
branch instruction or an interruption changes the
instruction sequence such that the instruction is not
executed.
Every instruction can cause an access exception
to be recognized because of instruction fetch.
Additionally, access exceptions associated with
instruction execution may occur because of an
access to an operand in storage.
An access exception due to fetching an
instruction is indicated when the first instruction
halfword cannot be fetched without encountering
the exception. When the first halfword of the
instruction has no access exceptions, access
exceptions may be indicated for additional
halfwords according to the instruction length
specified by the first two bits of the instruction;
however, when the operation can be performed
without accessing the second or third halfwords of
the instruction, it is unpredictable whether the
access exception is indicated for the unused part.
Since the indication of access exceptions for
instruction fetch is common to all instructions, it is
not covered in the individual instruction
definitions.
Except where otherwise indicated in the
individual instruction description, the following
rules apply for exceptions associated with an access
to an operand location. For a fetch-type operand,
access exceptions are necessarily indicated only for
that portion of the operand which is required for
completing the operation. It is unpredictable
whether access exceptions are indicated for those
portions of a fetch-type operand which are not
required for completing the operation. For a
store-type operand, access exceptions are
recognized for the entire operand even if the
operation could be completed without the use of
the inaccessible part of the operand. In situations
where the value of a store-type operand is defined
to be unpredictable, it is unpredictable whether an
access exception is indicated.
Whenever an access to an operand location can
cause an access exception to be recognized, the
word "access" is included in the list of program
exceptions in the description of the instruction.
This entry also indicates which operand can cause
the exception to be recognized and whether the
exception is recognized on a fetch or store access
to that operand location. Access exceptions are
recognized only for the portion of the operand as
defined by each particular instruction.
Chapter 6. Interruptions
6-15
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