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Program-Status-Word Format in
Be
Mode
The following is a summary of the functions of the
PSW fields in the BC mode. (See the figure "PSW
Format in BC Mode.")
Channel Masks 0-5: Bits 0-5 control whether the
CPU is enabled for I/O interruptions from
channels 0-5, respectively. When a bit is zero, the
associated channel cannot cause an I/O
interruption. When the bit is one, an interruption
condition at the channel can cause an I/O
interruption.
I/O Mask
(10):
Bit 6 controls whether the CPU is
enabled for I/O interruptions from channels 6 and
higher. When the bit is zero, these channels
cannot cause I/O
interruptions~
When the bit is
one~
I/O interruptions are subject to the
channel-mask bits of the corresponding channels in
control register 2: when a channel-mask bit is zero,
the associated channel cannot cause an I/O
interruption; when the channel-mask bit is one, an
interruption condition at the channel can cause an
interruption.
External Mask (EX): Bit 7 controls whether the
CPU is enabled for interruption by conditions
included in the external class. When the bit is
zero, an external interruption cannot occur. The
meaning is the same as in the EC mode.
PSW Key: Bits 8-11 form the access key for
storage references by the CPU. The meaning is the
same as in the EC mode.
Chan Masks
I
E
EC Mode (E): Bit 12, which controls the format
of the PSW and the mode of operation of the CPU,
is zero when the CPU is in the basic-control (BC)
mode.
Machine-Check Mask (M): Bit 13 controls
whether the CPU is enabled for interruption by
machine-check conditions. The meaning is the
same as in the BC mode.
Wait State (W): When bit 14 is one, the CPU is
waiting. The meaning is the same as in the BC
mode.
Problem State (P): When bit 15 is one, the CPU
is in the problem state. When bit 15 is zero, the
CPU is in the supervisor state. The meaning is the
same as in the BC mode.
Interruption Code: Bits 16-31 in the old PSW,
which is stored during a program, supervisor-call,
external, or I/O interruption, identify the cause of
the interruption. This field is not used or checked
in the current PSW. Whena new PSW is
introduced, the contents of this field are ignored.
Instruction-Length Code (ILC): The code in bit
positions 32 and 33 of the old PSW indicates the
length of the last-interpreted instruction when a
program or supervisor-call interruption occurs. See
the section "Instruction-Length Code" in Chapter
6, "Interruptions." When a new PSW is introduced,
the contents of this field are ignored.
Condition Code (CC): Bits 34 and 35 are the two
bits of the condition code. The meaning is the
same as in the BC mode.
0-5
0 X
Key
E M
W P
Interruption Code
0
6
8
12
16
31
IILC Icc
Prog
Mask
Instruction Address
32
34
36
40
63
PSW Format in BC Mode
4-6
IBM 4300 Processors Principles of Operation
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