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Resulting Condition Code:
o
Selected bits all zeros; or the mask is all zeros
1
Selected bits mixed zeros and ones
2
3
Selected bits all ones
Program Exceptions:
Access (fetch, operand
1)
Programming Note
An example of the use of TEST UNDER MASK is
given in Appendix A.
TRANSLATE
TR
°1(lsBl)s02(B2)
[SS]
I
B 1
I
/
~U
lOCi
l
°1
B2
/
0
8
16
20
32
36
47
The bytes of the first operand are used as eight-bit
arguments to reference a list designated by the
second-operand address. Each function byte
selected from the list replaces the corresponding
argument in the first operand.
The L field designates the length of only the
first operand.
The bytes of the first operand are selected orie
by one for translation, proceeding left to right.
Each argument byte is added to the initial
second-operand address. The addition is performed
following the rules for address arithmetic, with the
argument byte treated as an eight-bit unsigned
binary integer and extended with high-order zeros.
The sum is used as the address of the function byte,
which then replaces the original argument byte.
The operation proceeds until the first-operand
field is exhausted. The list is not altered unless an
overlap occurs.
When the operands overlap, the result is
obtained as if each result byte Were stored
immediately after the corresponding function byte
is fetched.
Access exceptions are recognized only for those
bytes in the second operand which are actually
required.
Condition Code: The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2; fetch and store,
operand 1)
7-36
IBM 4300 Processors Principles of Operation
Programming Notes
1. An example of the use of TRANSLATE is
given in Appendix A.
2. The instruction TRANSLATE may be used to
convert data from one code to another code.
3. The instruction may also be used to rearrange
data. This may be accomplished by placing a
pattern in the destination area, by designating
the pattern as the first operand of
TRANSLA TE, and by designating the data that
is to be rearranged as the second operand.
Each byte of the pattern contains an eight..,bit
number specifying the byte destined for this
position. Thus, when the instruction is
executed, the pattern selects the bytes of the
second operand in the desired order.
4. The fetch and subsequent store accesses to a
particular byte in the first-operand field do not
necessarily occur one immediately after the
other. Thus, this instruction cannot be safely
used to update a location in storage if the
possibility exists that another CPU or a channel
may also be updating the location. An example
of this effect is shown for the instruction OR
(01)
in the section "Multiprogramming and
Multiprocessing Examples '.' in Appendix A.
5. Because each eight-bit argument· byte is added
to the initial second-operand address to obtain
the address of a function byte, the list may
contain 256 bytes. In cases where it is known
that not all eight-bit argument values will
occur, it is possible to reduce the size of the
list.
I
6. Significant performance degradation is possible
when the second-operand address of
TRANSLA TE designates a location that is less
than 256 bytes to the left of a2,048-byte
boundary. This is because the machine may
perform a trial execution of the' instruction to
determine if the secondoperand actually
crosses the boundary.
TRANSLATE AND TEST
The bytes of the first operand .are· used as eight..;bit
arguments to select function bytes from a list
designated by the second-operand address. The,
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