Interruption Action - IBM 4300 Manual

psw-
Mask Bits
Mask in Ctrl Execution of
Bits Registers Instruction
Source Interruption ILC Identified
Identification
Code EC BC Reg, Bit Set by Old PSW
MACHINE CHECK
Locations 232-239 1
(old PSW 48,
new PSW 112)
Exigent condition
13
13 x terminated
Repressible cond
13
13 14, 4-7 x
unaffected 2
SUPERVISOR CALL Locations 138-139
(old PSW 32, in EC mode and
new PSW 96) 34-35 in BC mode
Instruction bits
00000000 ssssssss 1 ,2
completed
PROGRAM Locations 142-143
(old PSW 40, in EC mode and
new PSW 104) 42-43 in BC mode
Operation 00000000 pOOOOO01 1 ,2,3 suppressed
Pr
i
v i 1 eged oper 00000000 pOOOO010 1 ,2 suppressed
Execute 00000000 pOOOOO 11 2 suppressed
Protection 00000000 pOOO0100 1 ,2,3 suppressed or terminated
Addressing 00000000 pOOO0101 1 ,2,3 suppressed or terminated
Specification 00000000 pOOOO 110
0,1,2,3 suppressed or completed
Data 00000000 pOOOO 111
2,3 suppressed or terminated
Fixed-pt overflow 00000000 pOO01000 20 36 1 ,2 completed
Fixed-point divide 00000000 pOO0100l 1 ,2
suppressed or completed
Decimal overflow 00000000 pOO010l0 21 37
2,3 completed
Decimal divide 00000000 pOO01011 2,3 suppressed
Exponent overflow 00000000 pOO01100 1 ,2 completed
Exponent underflow 00000000 pOOOll0l 22 38 1 ,2 completed
Significance 00000000 pOO01110 23 39 1 ,2 completed
Floating-pt divide 00000000 pOO01111 1,2 suppressed
Special operation 00000000 p0010011 0, 1 2 suppressed
Page access
00000000 pOOll000 1 ,2,3 null ified
Page state 00000000 p0011010 2
suppressed
Page transition 00000000 pOOll011 2 suppressed
Monitor event
00000000 p1000000 8, 16+
2
completed
PER event
00000000 1nOnnnnn 3
1
'1,
9, 0-3
0,1,2,3 completed 4
Interruption Action (Part 1 of 2)
6-2 IB M 4300 Processors Principles of Operation