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second-operand address. Bits 12-15 of the
instruction are ignored.
The R
1
field of the instruction specifies an
even-odd pair of general registers and must
designate an even-numbered register. When Rl is
odd, a specification exception is recognized.
The second-operand address is not used to
address data; its low-order six bits indicate the
number of bit positions to be shifted. The
remainder of the address is ignored.
The first operand is treated as a 64-bit signed
binary integer. The sign position of the even
register remains unchanged. The leftmost position
of the odd register contains a numeric bit, which
participates in the shift in the same manner as the
other numeric bits. Zeros are supplied to the
vacated register positions on the right.
If one or more bits unlike the sign bit are shifted
out of bit position 1 of the even register, an
overflow occurs. The overflow causes a program
interruption when the fixed-point-overflow mask
bit is one.
Resulting Condition Code:
o
Result is zero
1
Result is less than zero
2
Result is greater than zero
3
Overflow
Program Exceptions:
Fixed-Point Overflow
Specification
Programming Notes
1. An example of the use of SHIFT LEFT
DOUBLE is given in Appendix A.
2. The eight shift instructions provide the
following three pairs of alternatives: left or
right, single or double, and signed or logical.
The signed shifts differ from the logical shifts
in that, in the signed shifts, overflow is
recognized, the condition code is set, and the
leftmost bit participates as a sign.
3. A zero shift amount in the two signed
double-shift operations provides a
double-length sign and magnitude test.
4. The. base register participating in the generation
of the second-operand address permits indirect
specification of the shift amount. A zero in the
B2 field indicates the absence of indirect shift
specification.
SHIFT LEFT DOUBLE LOGICAL
o
8
12
16
20
31
The double-length first operand is shifted left the
number of bits specified by the second-operand
address. Bits 12-15 of the instruction are ignored.
The R
1
field of the instruction specifies an
even-odd pair of general registers and must
designate an even-numbered register. When Rl is
odd, a specification exception is recognized.
The second -operand address is not used to
address data; its low-order six bits indicate the
number of bit positions to be shifted. The
remainder of the address is ignored.
All 64 bits of the first operand participate in the
shift. Bits shifted out of bit position 0 of the
even-numbered register are not inspected and are
lost. Zeros are supplied to the vacated register
positions on the right.
Condition Code: The code remains unchanged.
Program Exceptions:
Specification
SHIFT LEFT SINGLE
o
8
12
16
20
31
The numeric part of the first operand is shifted left
the number of bits specified by the second-operand
address. Bits 12-15 of the instruction are ignored.
The second -operand address is not used to
address data; its low-order six bits indicate the
number of bit positions to be shifted. The
remainder of the address is ignored.
The first operand is treated as a 32-bit signed
binary integer. The sign of the first operand
remains unchanged. All 31 numeric bits of the
operand participate in the left shift. Zeros are
supplied to the vacated register positions on the
right.
Chapter 7. General Instructions
7-29
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