Check-Stop State - IBM 4300 Manual

A storage-key error is not indicated when:
• Invalid CBC is detected in. the storage key of a
disconnected page
• Invalid CBC is detected in the page bits, the
page state, or the frame index of a page, whether
disconnected or not
• No look aside storage is provided for storage keys
All parts of the page descriptions are validated
manually by clear reset. On models which provide
lookaside storage with a' separate checking block
for the storage key of each connected or
addressable page, executing the instruction SET
STORAGE KEY sets new values for and validates
the storage key after a storage-key error has been
indicated. The instruction CONNECT PAGE may
validate the lookaside entry of a page frame which
previously had invalid CBC by using the values of
the storage key from the page-description entry.
I
No storage-key-error-uncorrected indication is
given when a machine check occurs during the
execution of DECONFIGURE PAGE,
DISCONNECT PAGE, LOAD FRAME INDEX,
MAKE ADDRESSABLE, and MAKE
UNADDRESSABLE.
Any machine-check condition which would
otherwise be indicated as a storage-key error
uncorrected is ignored if the access key is zero
when a fetch operation takes place. Depending on
the model, a storage-key error uncorrected mayor
may not be ignored if the access key is zero when a
store operation takes place or when the instruction
CLEAR PAGE is executed.
The CPU enters the check-stop state when
invalid CBC is detected in the page description for
page 0, and also when a page description is left in
an inconsistent state after an error occurs while the
page description is being updated.
Programming Note
Recovery from a storage-key error uncorrected
which cannot be successfully removed by issuing
SET STORAGE KEY may be attempted by issuing
DECONFIGURE PAGE to delete the page frame
and CONNECT PAGE to use another page frame.
The previous contents of the page are lost.
Invalid CBC in Registers
When invalid CBC is detected in a CPU register, a
machine-check condition may be recognized. CPU
registers include the general, floating-point, and
control registers, the current PSW, the time-of-day
clock, the CPU timer, and the clock comparator.
11-4 IBM 4300 Processors Principles of Operation
When a machine-check interrUption occurs,
whether or not it is due to invalid CBC in a CPU
register, the following actions affecting the CPU
registers, other than the time-of-day-clock, are
taken as part of the interruption.
1. The contents of the registers are saved in
assigned storage locations. Any register which
is in error is identified by a corresponding
validity bit of zero in the machine-check-
interruption code. Malfunctions detected during
register savingdo not result in additional
machine-check-interruption conditions; instead,
the correctness of all the information stored is
indicated by the appropriate setting of the
validity bits.
2. Registers with invalid CBC are then validated,
their actual contents being unpredictable.
CPU registers other than the time-of-day clock
are also validated manually by the clear-reset
function; programmed register validation is not
provided.
The time-of-day clock is not stored and is not
validated during a machine-check interruption, and
it has no corresponding validity bit. The clock
enters the error state when a malfunction is
detected in the clock. It is validated by
programming when a SET CLOCK instruction
changes the state of the clock from the error state
to the set state. The clock is also validated
manually by a power-on reset.
Check-Stop State
In certain situations it is impossible or undesirable
to continue operation when a machine error occurs.
In these cases, the CPU may enter the check-stop
state, which is indicated by the check-stop
indicator.
In general, the CPU may enter the check-stop
state whenever an uncorrectable error or other
malfunction occurs and the machine is unable to
recognize a specific machine-check-interruption
condition.
The CPU always enters the check-stop state if
any of the following conditions exists:
• PSW bit 13 is zero and an exigent
machine-check condition is generated.
• During the execution of an interruption due to
one exigent machine-check condition, another
exigent machine-check condition is detected.
• During a machine-check interruption, the
machine-check-interruption code cannot be
stored successfully or the new PSW be fetched
successfully.