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Add; Add Halfword; Add Logical; And - IBM 4300 Manual

Processors principles of operation for ecps: vse mode
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ADD
AR
'lA'
o
8
12
15
A
[RX]
, 5A '
I
R 1
I
X2
I
B2
o
8
12
16
20
31
The second operand is added to the first operand,
and the sum is placed in the first-operand location.
The operands and the sum are treated as 32-bit
signed binary integers.
An overflow causes a program interruption when
the fixedpointoverflow mask bit is one.
Resulting Condition Code:
o
Sum is zero
1
Sum is less than zero
2
Sum is greater than zero
3
Overflow
Program Exceptions:
Access (fetch, operand 2 of A only)
Fixed-Point Overflow
ADD HALFWORD
AH
[RX]
'4A'
o
8
12
16
20
31
The second operand is added to the first operand,
and the sum is placed in the first-operand location.
The second operand is two bytes in length and is
treated as a 16-bit signed binary integer. The first
operand and the sum are treated as 32-bit signed
binary integers.
An overflow causes a program interruption when
the fixed-point-overflow mask bit is one.
Resulting Condition Code:
o
Sum is zero
1
Sum is less than zero
2
Sum is greater than zero
3
Overflow
Program Exceptions:
Access (fetch, operand 2)
Fixed-Point Overflow
Programming Note
An example of the use of ADD HALFWORD is
given in Appendix A.
ADD LOGICAL
ALR
o
8
12
15
o
8
12
16
20
31
The second operand is added to the first operand,
and the sum is placed in the first-operand location.
The operands and the sum are treated as 32-bit
unsigned binary integers.
Resulting Condition Code:
o
Sum is zero, with no carry
1
Sum is not zero, with nQ carry
2
Sum is zero, with carry
3
Sum is not zero, with carry
Program Exceptions:
Access (fetch, operand 2 of AL only)
AND
NR
, 14'
o
8
12
15
N
[RX]
o
8
12
16
20
31
Chapter 7. General Instructions
7-7

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