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Bits 8-15 of the instruction, with eight
high-order zeros appended, are placed. in the
supervisor-call interruption code that is stored in
the course of the interruption. See
"SupervisQr-Call Interruption" in Chapter 6,
"Interruptions. "
A serialization function is performed. CPU
operation is delayed until all previous storage
accesses by this CPU to storage have been
completed, as observed by channels and and other
CPUs. No subsequent instructions or their
operands are accessed by this CPU until the
execution of this instruction is completed.
Condition Code: The code remains unchanged and
is saved as part of the old PSW. A new condition
code is loaded as part of the supervisor-call
interruption.
Program Exceptions: None.
TEST AND SET
o
8
16
20
31
The leftmost bit (bit position 0) of the byte located
at the second-operand address is used to set the
condition code, and then the byte is set to all ones.
Bits 8-15 of the instruction are ignored.
The byte in storage is set to all ones as it is
fetched for the testing of bit position O. No access
by another CPU to this location is permitted
between the moment of fetching and the moment
of storing all ones.
A serialization function is performed before the
byte is fetched and again after the storing of all
ones. CPU operation is delayed until all previous
accesses by this CPU to storage have been
completed, as observed by channels and other
CPUs, and then the byte is fetched. No subsequent
instructions or their operands are accessed by this
CPU until the all-ones value has been placed in
storage, as observed by channels and other CPUs.
Resulting Condition Code:
o
Leftmost bit of byte specified was zero
1
Leftmost bit of byte specified was one
2
3
Program Exceptions:
Access (fetch and store, operand 2)
Programming Notes
1. TEST AND SET may be used for controlled
sharing of a common storage area by more than
one program. To accomplish thiS, bit position 0
of a byte must be designated as the control bit.
The desired interlock can be achieved by
establishing a program convention in which a
zero in the bit position indicates that the
common area is available but a one means that
the area is being used. Each using program
then must examine this byte by means of TEST
AND SET before making access to the common
area. If the test sets condition code 0, the area
is available for use; if it sets condition code 1,
the area cannot be used. Because TEST AND
SET permits no other CPU access to the test
byte between the moment of fetching (for
testing) and the moment of storing all ones
(setting), the possibility is eliminated of a
second program testing the byte before the first
program is able to set it.
2.
It
should be noted that TEST AND SET does
not interlock against storage accesses by
channels.
TEST UNDER MASK
TM
[S I ]
1911
o
8
16
20
31
A mask is used to select bits of the first operand,
and the result is indicated in the condition code.
The byte of immediate data, 1
2 ,
is used as an
eight-bit mask. The bits of the mask are made to
correspond one for one with the bits of the byte in
storage designated by the first-operand address.
A mask bit of one indicates that the storage bit
is to be tested. When the mask bit is zero, the
storage bit is ignored. When all storage bits thus
selected are zero, condition code 0 is set.
Condition code 0 is also set when the mask is all
zeros. When the selected bits are all ones,
condition code 3 is set; otherwise, the code is set to
l.
Access exceptions associated with the storage
operand are recognized for one byte even when the
mask is all zeros.
Chapter 7. General Instructions
7-35
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