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The second operand is placed in the first-operand
location.
For MVC, each operand is processed left to
right. When the operands overlap, the result is
obtained as if the operands were processed one
byte at a time and each result byte were stored
immediately after the necessary operand byte is
fetched.
For MVI, the first operand is one byte inlength,
and only one byte is stored.
Condition Code: The code remains unchanged.
Program Exceptions:
Access (fetch, operand
2
of MVC; store, operand
1, MVI and MVC)
Programming Notes
1. Examples of the use of the MOVE instructions
are given in Appendix A.
2. It is possible to propagate one byte through an
entire field by having the first operand start
one byte to the right of the second operand.
MOVE INVERSE
MVCIN
[55]
L--'_E8_'
----L-_ _
l
---,-1_B_1
--,-1_~_1
---I1_B_2
--,-1_~iJ
o
8
16
20
32
36
47
The second operand is placed in the first-operand
location with the left-to-right sequence of the bytes
inverted.
The first-operand address designates the leftmost
byte of the first operand. The second-operand
address designates the rightmost byte of the second
operand. Both operands have the same length.
The result is obtained as if the second operand
were processed from right to left and the first
operand· from left to right. The second operand
may wrap around from location 0 to location
16,777,215. The first operand may wrap around
from location 16,777,215 to location O.
When the operands overlap by more than one
byte, the contents of the overlapped portion of the
result field are unpredictable.
Condition Code: The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2; store, operand 1)
7-22
IBM 4300 Processors Principles of Operation
Programming Notes
1. The contents of each byte moved remain
unchanged.
2. MOVE INVERSE is the only SS-format
instruction for which the second-operand
address designates the rightmost, instead of the
leftmost, byte of the second operand.
MOVE LONG
MVCl
[RR]
'OE'
o
8
12
15
The second operand is placed in the first-operand
location, provided overlapping of operand locations
does not affect the final contents of the
first-operand location. The remaining rightmost
byte positions, if any, of the first-operand location
are filled with padding bytes.
The Rl and R2 fields each specify an even-odd
pair of general registers and must designate an
even-numbered register; otherwise, a specification
exception is recognized.
The location of the leftmost byte of the first
operand and second operand is designated by bits
8-31 of the general registers specified by the R
1
and
R2
fields, respectively. The number of bytes in
the first-operand and second-operand locations is
specified by bits 8-31 of general registers R
1
+
1
and R
2
+
1, respectively. Bit positions 0-7 of
register
R2
+
1 contain the padding byte. The
contents of bit positions 0-7 of registers R
l'
R
2 ,
and R
1
+
1 are ignored.
Graphically, the contents of the registers just
described are as follows:
R1
I11111111I
First-Operand Address
o
8
31
R1+1
I11111111I
First-Operand length
o
8
31
1111111111
Second-Operand Addressl
o
8
31
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