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part would be less than zero but the characteristic
of the high-order part is zero or greater.
The result fraction is zero when the
intermediate-sum fraction, including the guard
digit, is zero. With a zero result fraction, the
action depends on the setting of the significance
mask bit. If the significance mask bit is one, no
normalization occurs, the intermediate and final
result characteristics are the same, and a program
interruption for significance takes place. If the
significance mask bit is zero, the program
interruption does not occur; instead, the result is
made a true zero.
The Rl field for AER, AE, ADR, and AD, and
the R2 field for AER and ADR must designate
register 0, 2, 4, or 6. The Rl and R2 fields for
AXR must designate register 0 or 4. Otherwise, a
specification exception is recognized.
Resulting Condition Code:
o
Result fraction is zero
1
Result is less than zero
2
Result is greater than zero
3
Program Exceptions:
Access (fetch, operand 2 of AE and AD only)
Exponent Overflow
Exponent Underflow
Significance
Specification
Programming Notes
1. Interchanging the two operands in a
floating-point addition does not affect the value
of the sum.
2. The ADD NORMALIZED instructions
normalize the sum but not the operands. Thus,
if one or both operands are unnormalized,
precision may be lost during fraction alignment.
ADD UNNORMALIZED
[RR, Short Operands]
o
8
12
15
AU
[RX, Short Operands]
o
8
12
16
20
31
[RR, Long Operands]
o
8
12
15
AW
R1,D2(X2,B2)
[RX, Long Operands]
I
6E
I
I
R 1
I
X2
I
B2
D2
o
8
12
16
20
31
The second operand is added to the first operand,
and the unnormalized sum is placed in the
first-operand location.
The execution of ADD UNNORMALIZED is
identical to that of ADD NORMALIZED, except
that:
1. When no carry is· present after the addition, the
intermediate-sum fraction is truncated to the
proper result-fraction length without a left shift
to eliminate leading hexadecimal zeros and
without the corresponding reduction of the
characteristic.
2. Exponent underflow cannot occur.
3. The guard digit does not participate in the
recognition of a zero result fraction. A zero
result fraction is recognized when the fraction,
that is, the intermediate-sum fraction, excluding
the guard digit, is zero.
The R
1
and R2 fields must designate register 0,
2, 4, or 6; otherwise, a specification exception is
recognized.
Resulting Condition Code:
o
Result fraction is zero
1
Result is less than zero
2
Result is greater than zero
3
Program Exceptions:
Access (fetch, operand 2 of AU and AW only)
Exponent Overflow
Significance
Specification
Programming Note
Except when the result is made a true zero, the
characteristic of the result of ADD
UNNORMALIZED is equal to the greater of the
two operand characteristics, increased by one if the
fraction addition produced a carry.
Chapter 9. Floating-Point Instructions
9-7
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