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Start I/O - IBM 4300 Manual

Processors principles of operation for ecps: vse mode
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START I/O
SID
°2(B2)
[S]
9COO
I
B2
I
°2
0
16
20
31
START I/O FAST RELEASE
SIOF
0(B2)
[S]
9C01
I
B2
I
°2
0
16
20
31
A write, read, read backward, control, or sense
operation is initiated with the addressed I/O device
and subchannel. Bits 8-14 of the instruction are
ignored.
Either an SIO or SIOF function is performed,
depending on the instruction, the channel, and the
block-multiplexing control, bit 0 of control register
O.
The instruction START I/O always causes the
SIO function to be performed, as does ST ART I/O
FAST RELEASE when the block-multiplexing-
control bit is zero. When the bit is one, START
110
FAST RELEASE may, depending on the
channel, cause either the SIO or the SIOF function
to be performed.
Bits 16-31 of the second-operand address
identify the channel, subchannel, and 110 device to
which the instruction applies. The CAW, at
location 72, contains the subchannel key and the
address of the first CCW. This CCW specifies the
operation to be performed, the storage area to be
used, and the action to be taken when the
operation is completed.
For the SIO function, the 1/0 operation is
initiated if the addressed 110 device and
subchannel are available, the channel is available or
interruption-pending, and errors or exceptional
situations have not been detected. The I/O
operation is not initiated when the addressed part
of the 110 system is in any other state or when the
channel or device detects any error or exceptional
situations during execution of the instruction.
For the SIOF function, the I/O operation is
initiated if the subchannel is available, the channel
is available or interruption-pending, and errors or
exceptional situations have not been detected. Tbe
I/O operation is not initiated when the subchannel
and channel are in any other state or when the
channel or device detects any error or exceptional
situation during execution of the instruction. . The
device state or device-detected errors are not
relevant during instruction execution but are
indicated in a CSW stored during a subsequent
interruption.
When the channel is available or interruption-
pending, and the subchannel is available before the
execution of the instruction, the following
situations cause a CSW to be stored. How the
CSW is stored depends on whether an SIO or SIOF
function is performed. The SIO function causes
the status portion of the CSW to be replaced by a
new set of status bits. The status bits pertain to
the device addressed by the instruction. The
contents of the other fields of the CSW are not
changed. When the SIOF function is performed,
the first situation causes the same action as for the
SIO function; also, the control-unit and device
state may be tested, and so situation 5 may cause
the same action as for the SIO function, or the
situation may be indicated in a subsequent 1/0
interruption during which the entire CSW will be
stored. The remaining situations for the SIOF
function will be indicated in a subsequent
interruption, during which the entire CSW will be
stored.
1. The channel detects a programming error in the
contents of the CAW or detects an equipment
error during execution of the instruction. The
CSW identifies the error.
If
selection of the
device occurred prior to detection of the error
or if the error condition was detected during
the selection of the device, the device status is
indicated in the CSW.
2. The channel detects a programming error
associated with the first CCW or, for the SIOF
function, the channel detects an equipment
error after completion of the instruction. The
CSW identifies the error.
If
selection of the
device occurred prior to detection of the error,
or if the error condition was detected during
the selection of the device, the device status is
indicated in the CSW.
3. An immediate operation was executed, and
either (1) no command chaining is specified
and no command retry occurs, or (2) chaining
is suppressed because of unusual situations
detected during the operation. In the CSW, the
channel-end bit is one, the busy bit is zero, and
other status may be indicated. The PCI bit is
one if PCI was specified in the first CCW. The
110
operation is initiated, but no information
Chapter 12. Input/Output Operations
12-21

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