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Condition Code: The code may be set by the
target instruction.
Program Exceptions:
Access (fetch, target instruction)
Execute
Specification
Programming Notes
1. An example of the use of EXECUTE is given
in Appendix A.
2. The ORing of eight bits from the general
register with the designated instruction permits
indirect length, index, mask, immediate-data,
and register specification.
3. The fetching of the target instruction is
considered to be an instruction fetch for
purposes of program-event recording and for
purposes of reporting access exceptions.
4. An access or specification exception may be
caused by EXECUTE or by the target
instruction.
S. When an interruptible instruction is made the
target of EXECUTE, the program normally
should not designate any register updated by
the interruptible instruction as the R
1,
X
2 ,
or
B2
register for EXECUTE, since on resumption
of execution after an interruption, or if the
instruction is refetched without an interruption,
the updated values of these registers will be
used in the execution of EXECUTE. Similarly,
the program should normally not let the
destination field of an interruptible instruction
include the location of the EXECUTE, since
the new contents of the location may be
interpreted when resuming execution.
INSERT CHARACTER
IC
R1,D2(X2,B2)
[RX]
'43'
I
R1
I
X2
I
B2
D2
0
8
12
16
20
31
The byte at the second -operand location is inserted
into bit positions 24-31 of the general register
designated by the R
1
field. The remaining bits in
the register remain unchanged.
Condition Code: The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2)
7-18
IBM 4300 Processors Principles of Operation
INSERT CHARACTERS UNDER MASK
ICM
R1,M3,D2(B2)
[RS]
'BF'
I
R1
I
M3
I
B2
D2
0
8
12
16
20
31
Bytes from contiguous locations beginning at the
second-operand address are inserted into the
first-operand location under control of a mask.
The contents of the M
3
field are used as a mask.
These four bits, left to right, correspond one for
one with the four bytes, left to right, of the general
register designated by the R
1
field. The byte
positions corresponding to ones in the mask are
filled, left to right, with bytes from successive
storage locations beginning at the second-operand
address. When the mask is not zero, the length of
the second operand is equal to the number of ones
in the mask. The bytes in the general register
corresponding to zeros in the mask remain
unchanged.
The resulting condition code is based on the
mask and on the value of the bits insetted. When
the mask is zero or when all inserted bits are zeros,
the condition code is set to O. When the inserted
bits are not all zeros, the code is set according to
the leftmost bit of the storage operand: if this bit is
one, the code is set to 1; if this bit is zero, the code
is set to 2.
When the mask is not zero, exceptions associated
with storage-operand access are recognized only for
the number of bytes specified by the mask. When
the mask is zero, access exceptions are recognized
for one byte.
Resulting Condition Code:
o
All inserted bits are zeros, or mask is zero
1
Leftmost bit of the inserted field is one
2
Leftmost bit of the inserted field is zero, and
not all inserted bits are zeros
3
Program Exceptions:
Access (fetch, operand 2)
Programming Notes
1. Examples of the use of INSERT
CHARACTERS UNDER MASK are given in
Appendix A.
2. The condition code for INSERT
CHARACTERS UNDER MASK (ICM) is
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